TY - GEN
T1 - Spin wave based full adder
AU - Mahmoud, Abdulqader
AU - Vanderveken, Frederic
AU - Ciubotaru, Florin
AU - Adelmann, Christoph
AU - Cotofana, Sorin
AU - Hamdioui, Said
PY - 2021
Y1 - 2021
N2 - Spin Waves (SWs) propagate through magnetic waveguides and interfere with each other without consuming noticeable energy, which opens the road to new ultra-low energy circuit designs. In this paper we build upon SW features and propose a novel energy efficient Full Adder (FA) design consisting of 1 Majority and 2 XOR gates, which outputs Sum and Carry − out are generated by means of threshold and phase detection, respectively. We validate our proposal by means of MuMax3 micromagnetic simulations and we evaluate and compare its performance with state-of-the-art SW, 22 nm CMOS, Magnetic Tunnel Junction (MTJ), Spin Hall Effect (SHE), Domain Wall Motion (DWM), and Spin-CMOS implementations. Our evaluation indicates that the proposed SW FA consumes 22.5% and 43% less energy than the direct SW gate based and 22 nm CMOS counterparts, respectively. Moreover it exhibits a more than 3 orders of magnitude smaller energy consumption when compared with state-of-the-art MTJ, SHE, DWM, and Spin-CMOS based FAs, and outperforms its contenders in terms of area by requiring at least 22% less chip real-estate.
AB - Spin Waves (SWs) propagate through magnetic waveguides and interfere with each other without consuming noticeable energy, which opens the road to new ultra-low energy circuit designs. In this paper we build upon SW features and propose a novel energy efficient Full Adder (FA) design consisting of 1 Majority and 2 XOR gates, which outputs Sum and Carry − out are generated by means of threshold and phase detection, respectively. We validate our proposal by means of MuMax3 micromagnetic simulations and we evaluate and compare its performance with state-of-the-art SW, 22 nm CMOS, Magnetic Tunnel Junction (MTJ), Spin Hall Effect (SHE), Domain Wall Motion (DWM), and Spin-CMOS implementations. Our evaluation indicates that the proposed SW FA consumes 22.5% and 43% less energy than the direct SW gate based and 22 nm CMOS counterparts, respectively. Moreover it exhibits a more than 3 orders of magnitude smaller energy consumption when compared with state-of-the-art MTJ, SHE, DWM, and Spin-CMOS based FAs, and outperforms its contenders in terms of area by requiring at least 22% less chip real-estate.
KW - Spin-wave
KW - Spin-wave computation paradigm
KW - Full adder
KW - Energy
KW - Delay
KW - Area
UR - http://www.scopus.com/inward/record.url?scp=85109007773&partnerID=8YFLogxK
U2 - 10.1109/ISCAS51556.2021.9401524
DO - 10.1109/ISCAS51556.2021.9401524
M3 - Conference contribution
AN - SCOPUS:85109007773
T3 - 2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
BT - 2021 IEEE International Symposium on Circuits and Systems (ISCAS)
PB - IEEE
CY - Piscataway
T2 - 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
Y2 - 22 May 2021 through 28 May 2021
ER -