Abstract
CMOS downscaling has provided the means to efficiently process the huge raw data resulted from the information technology revolution. However, this becomes more difficult because of leakage, reliability, and cost walls. To keep the pace with the exploding market needs at affordable cost, novel alternative technologies are under investigation; one of them is Spin Wave (SW), which is the collective excitation of the electron spins in the ferromagnetic materials. SW stands apart as one of the most promising avenues because of its ultralow energy consumption and high scalability. This thesis: a) develops and designs spin wave based logic gates and circuits, and b) investigates the requirements for spin wave technology to outperform CMOS technology from energy efficiency point of view.
Logic gate: SW circuit design requires the availability of SW logic gates to possess fanout capabilities. Therefore, we propose and validate novel fanout enabled spin wave logic gates including (N)AND, (N)OR, X(N)OR, and majority gates. In addition, we present and validate novel nbit multifrequency data parallel spin wave logic gates, i.e., SWs with different frequencies propagate in the same waveguide while interfering with similar frequency SWs only. Moreover, we examine a SW 3input Majority gate working under continuous and pulse mode operation regimes. Furthermore, we present and validate how pulse mode operation enables Wave Pipelining (WP) within SW.
Circuits: We develop, design, and validate three major circuits; namely an adder, a multiplier, and a compressor. These make use of SW gate cascading. Firstly, we introduce and validate SW accurate and approximate full adders; the approximate full adder consumes 55% less energy than the accurate full adder but it has 25% error rate making it suitable for error tolerant applications. We also propose a nonbinary SW computing paradigm which we use to build a nonbinary SW adder. Then we develop SW accurate and approximate 4:2 compressor; the approximate compressor consumes 46% less energy than the accurate compressor but it has 31% error rate. Finally, we design 2bit inputs accurate and approximate multiplier; the approximate multiplier consumes 64% less energy than the accuratemultiplier but it has 25% error rate.
SW Technology Requirements: We are interested in assessing the technological development horizon that needs to be reached to make SW circuits outperform CMOS counterparts in terms of energy efficiency. We performace reverse engineering alike analysis to determine transducer delay and power consumption upper bounds that can place SW circuits in the leading position. To this end, we compute the maximum transducer delay and power consumption of a 32bit BrentKung adder that could potentially enable a SW implementation able to outperform its 7 nm CMOS counterpart. Our evaluations indicate that 31nW is the maximum transducer power consumption for which a 32bit BrentKung SW implementation can outperform its 7nm CMOS counterpart in term of energy efficiency.
Logic gate: SW circuit design requires the availability of SW logic gates to possess fanout capabilities. Therefore, we propose and validate novel fanout enabled spin wave logic gates including (N)AND, (N)OR, X(N)OR, and majority gates. In addition, we present and validate novel nbit multifrequency data parallel spin wave logic gates, i.e., SWs with different frequencies propagate in the same waveguide while interfering with similar frequency SWs only. Moreover, we examine a SW 3input Majority gate working under continuous and pulse mode operation regimes. Furthermore, we present and validate how pulse mode operation enables Wave Pipelining (WP) within SW.
Circuits: We develop, design, and validate three major circuits; namely an adder, a multiplier, and a compressor. These make use of SW gate cascading. Firstly, we introduce and validate SW accurate and approximate full adders; the approximate full adder consumes 55% less energy than the accurate full adder but it has 25% error rate making it suitable for error tolerant applications. We also propose a nonbinary SW computing paradigm which we use to build a nonbinary SW adder. Then we develop SW accurate and approximate 4:2 compressor; the approximate compressor consumes 46% less energy than the accurate compressor but it has 31% error rate. Finally, we design 2bit inputs accurate and approximate multiplier; the approximate multiplier consumes 64% less energy than the accuratemultiplier but it has 25% error rate.
SW Technology Requirements: We are interested in assessing the technological development horizon that needs to be reached to make SW circuits outperform CMOS counterparts in terms of energy efficiency. We performace reverse engineering alike analysis to determine transducer delay and power consumption upper bounds that can place SW circuits in the leading position. To this end, we compute the maximum transducer delay and power consumption of a 32bit BrentKung adder that could potentially enable a SW implementation able to outperform its 7 nm CMOS counterpart. Our evaluations indicate that 31nW is the maximum transducer power consumption for which a 32bit BrentKung SW implementation can outperform its 7nm CMOS counterpart in term of energy efficiency.
Original language  English 

Qualification  Doctor of Philosophy 
Awarding Institution 

Supervisors/Advisors 

Award date  14 Jun 2022 
Print ISBNs  9789464195255 
DOIs  
Publication status  Published  2022 
Keywords
 Spin wave
 Logic Gate
 Circuit design
 Fanout
 Cascading
 Adder
 Multiplier
 Accurate computing
 Approximate computing
 Digital computing
 Analog computing
 Parallelism
 Wavepipelining
 Energy
 Area