Structured Test Development Approach for Computation-in-Memory Architectures

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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Abstract

Testing of Computation-in-Memory (CIM) designs based on emerging non-volatile memory technologies, such as resistive RAM (RRAM), is fundamentally different from testing traditional memories. Such designs allow not only for data storage (i.e., memory configuration) but also for the execution of logical and arithmetic operations (i.e., computing configuration). Therefore, not only significant design changes are needed in the memory array and/or in the peripheral circuits, but also new fault models and test approaches are needed. Moreover, RRAM-based CIM makes use of non-linear non-volatile devices making the defect modeling with traditional linear resistor inappropriate for such device defects. Hence, even the way of doing defect modeling has to change. This paper discusses a structured test development approach for RRAM-based CIM and highlights the test challenges and how testing CIM dies is different from the traditional way of testing logic and memory. Methods for defect modeling, fault modeling, and test development will be discussed. The paper demonstrates that unique faults can occur in the CIM die while in the computation configuration and that these faults cannot be detected by just testing the CIM die in the memory configuration. Moreover, it shows that testing the CIM die in the computation configuration reduces the overall test time while improving the outgoing product quality. Finally, the paper presents an outlook on the future of structured CIM test development.
Original languageEnglish
Title of host publicationProceedings of the 2022 IEEE International Test Conference in Asia (ITC-Asia)
EditorsC. Ceballos
Place of PublicationPiscataway
PublisherIEEE
Pages61-66
Number of pages6
ISBN (Electronic)978-1-6654-5523-7
ISBN (Print)978-1-6654-5524-4
DOIs
Publication statusPublished - 2022
Event 2022 IEEE International Test Conference in Asia (ITC-Asia) - Taipei, Taiwan
Duration: 24 Aug 202226 Aug 2022

Conference

Conference 2022 IEEE International Test Conference in Asia (ITC-Asia)
Country/TerritoryTaiwan
CityTaipei
Period24/08/2226/08/22

Bibliographical note

Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care

Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Keywords

  • computation-in-memory (CIM)
  • device-aware
  • defect
  • fault
  • test
  • RRAM
  • ReRAM

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