Supply-Insensitive Frequency Synthesis for an LDO-Free Powering Scheme in SoCs

Research output: ThesisDissertation (TU Delft)

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Abstract

The scaling of CMOS technology in deep submicron process nodes is accompanied by the integration of more and more functional blocks of a system, whether digital or analog/RF, onto the same chip (i.e., system-onchip, SoC). These blocks would also place different requirements on their power supplies. To provide various static or dynamically controlled supply voltages needed by the SoC, a dedicated power management unit (PMU) is typically deployed. Following the same trend of system integration, implementing the PMU on-die is also highly desired. The core of a PMU consists of several sets of voltage regulators that convert the output level of the energy source to the multiple supply voltages required by the integrated system. The DC-DC converters (switching regulators) and the low-dropout (LDO) linear regulators are normally employed in cascade for high power efficiency and for suppressing ripple amplitude demanded by the supply sensitive blocks, respectively. Although much effort has been devoted to the research on the design of fully integrated, or the so-called ‘capacitor-less’ LDOs, little has been done for the co-analysis and co-design of these LDOs with the load circuitry they power. Frequency synthesizers have found wide applications in various systems. The phase-locked loop, as one of the most commonly used frequency synthesis techniques, modulates the oscillator in a feedback manner to generate the desired loop output. The first part of this thesis (Chapters 2 and 3) focuses on the power efficiency of the capacitor-less LDO when powering a PLL. Since the PLL, especially its oscillator, is sensitive to the supply perturbations, the LDO should provide a high power supply rejection (PSR) at the ripple frequency, which could be in the range of 153 154 Summary several to tens of megahertz for integrated DC-DC converters, with a low output noise. The dropout voltage of the LDO is then determined by the required PSR, consuming extra voltage headroom and degrading the efficiency of the system. The tolerable output noise generally limits the minimum quiescent current consumed by the error amplifier (EA) and the feedback resistors in the LDO. Owning to the stringent requirement of the supply noise imposed by the oscillator in order to preserve its inherent phase noise performance, the efficiency of the corresponding LDO would be further degraded by a large factor due to its quiescent current consumption. Based on the analysis above, it deems beneficial to power the PLL directly from the output of DC-DC converters. Taking this step further, different scenarios of powering the SoC are also identified and briefly discussed at the end of the first part. To enable the proposed direct connection, the modules in the PLL should be able to tolerate the output ripples from such converters. In the second part of this thesis (Chapters 4 and 5), a fractional-N digitally intensive PLL (DPLL) architecture capable of maintaining its performance under a large (i.e., 50mVpp) supply ripple is developed. The digital implementation is selected due to its ability to incorporate various digital calibration techniques with relative ease. The supply pushing of the LC oscillator used in the DPLL is suppressed by the proposed feed-forward ripple replication and cancellation technique, which replicate the supply ripple to the gate of its tail current source with a proper gain, stabilizing the oscillator tail current, and correspondingly, the oscillation swing. The optimal gain is calibrated on-chip through amplifying the oscillation amplitude variation and locating the control setting corresponding to the minimum value. The time error between the reference and the divided output of the oscillator is linearly converted into voltage domain through the current-mode supply insensitive slope generator, with its input range being halved by resampling the output of the multi-modulus divider (MMDIV), driven by second-order .. modulation, with both edges of the oscillation signal. The output of a current DAC operating in parallel is also cascaded with the slope generator during phase detection to limit the dynamic range of the SAR ADC used to digitize the phase error. A low-power ripple pattern estimation and cancellation algorithm is also inserted at the ADC output to remove 155 the effect of the output delay perturbations of loop components under the supply ripple. Employing all these techniques, the proposed DPLL demonstrates, for the first time ever, the acceptable performance while operating under a large 50mVpp supply ripple.
Original languageEnglish
QualificationDoctor of Philosophy
Awarding Institution
  • Delft University of Technology
Supervisors/Advisors
  • Staszewski, R.B., Supervisor
  • Babaie, M., Advisor
Award date30 Mar 2022
DOIs
Publication statusPublished - 2022

Keywords

  • Frequency synthesizer
  • ital phase-locked loop (DPLL)
  • LC oscillator
  • LDO
  • PMU
  • SoC

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