Synthesizing HDL to Memristor Technology: A Generic Framework

Hoang Anh Du Nguyen, Lei Xie, Mottaqiallah Taouil, Said Hamdioui, Koen Bertels

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

8 Citations (Scopus)

Abstract

Memristors are emerging devices with huge potentials. It has been shown that they can be used not only to design non-volatile memories, but also logic circuits. In the latter, memristor devices are stacked on a CMOS circuit which
generates the required control signals needed by the memristors to perform the required functionality. This paper sets a step towards automating this process; it proposes a generic synthesis framework to map logic circuits on memristor
crossbar. The framework takes HDL descriptions as input and generates both its memristor circuitry and its associated CMOS control. The framework consists of three phases: (i) netlist generation, (ii) partition and mapping, and (iii) placement and routing. To illustrate the framework, a combinational and a sequential circuit are investigated. The results are validated using HSPICE simulations.
Original languageEnglish
Title of host publication2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
EditorsW. Zhao, C.A. Moritz
Place of PublicationNew York
PublisherAssociation for Computing Machinery (ACM)
Pages43-48
Number of pages6
ISBN (Electronic)978-1-4503-4330-5
DOIs
Publication statusPublished - 2016
Event2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - Beijing, China
Duration: 18 Jul 201620 Jul 2016

Conference

Conference2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
Abbreviated titleNANOARCH 2016
CountryChina
CityBeijing
Period18/07/1620/07/16

Keywords

  • Memristors
  • Hardware design languages
  • Logic gates
  • IP networks
  • Radiation detectors
  • Routing
  • Wires

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