Synthesizing HDL to Memristor Technology: A Generic Framework

Hoang Anh Du Nguyen; Lei Xie; Mottaqiallah Taouil; Said Hamdioui; Koen Bertels

doi:10.1145/2950067.2950098

Synthesizing HDL to Memristor Technology: A Generic Framework

Hoang Anh Du Nguyen, Lei Xie, Mottaqiallah Taouil, Said Hamdioui, Koen Bertels

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

11 Citations (Scopus)

Abstract

Memristors are emerging devices with huge potentials. It has been shown that they can be used not only to design non-volatile memories, but also logic circuits. In the latter, memristor devices are stacked on a CMOS circuit which
generates the required control signals needed by the memristors to perform the required functionality. This paper sets a step towards automating this process; it proposes a generic synthesis framework to map logic circuits on memristor
crossbar. The framework takes HDL descriptions as input and generates both its memristor circuitry and its associated CMOS control. The framework consists of three phases: (i) netlist generation, (ii) partition and mapping, and (iii) placement and routing. To illustrate the framework, a combinational and a sequential circuit are investigated. The results are validated using HSPICE simulations.

Original language	English
Title of host publication	2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
Editors	W. Zhao, C.A. Moritz
Place of Publication	New York
Publisher	Association for Computing Machinery (ACM)
Pages	43-48
Number of pages	6
ISBN (Electronic)	978-1-4503-4330-5
DOIs	https://doi.org/10.1145/2950067.2950098
Publication status	Published - 2016
Event	2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - Beijing, China Duration: 18 Jul 2016 → 20 Jul 2016

Conference

Conference	2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
Abbreviated title	NANOARCH 2016
Country/Territory	China
City	Beijing
Period	18/07/16 → 20/07/16

Keywords

Memristors
Hardware design languages
Logic gates
IP networks
Radiation detectors
Routing
Wires

Access to Document

10.1145/2950067.2950098

Cite this

@inproceedings{eca0ee2b58294a71b46d7adb282dcbf0,

title = "Synthesizing HDL to Memristor Technology: A Generic Framework",

abstract = "Memristors are emerging devices with huge potentials. It has been shown that they can be used not only to design non-volatile memories, but also logic circuits. In the latter, memristor devices are stacked on a CMOS circuit whichgenerates the required control signals needed by the memristors to perform the required functionality. This paper sets a step towards automating this process; it proposes a generic synthesis framework to map logic circuits on memristorcrossbar. The framework takes HDL descriptions as input and generates both its memristor circuitry and its associated CMOS control. The framework consists of three phases: (i) netlist generation, (ii) partition and mapping, and (iii) placement and routing. To illustrate the framework, a combinational and a sequential circuit are investigated. The results are validated using HSPICE simulations.",

keywords = "Memristors, Hardware design languages, Logic gates, IP networks, Radiation detectors, Routing, Wires",

author = "{Du Nguyen}, {Hoang Anh} and Lei Xie and Mottaqiallah Taouil and Said Hamdioui and Koen Bertels",

year = "2016",

doi = "10.1145/2950067.2950098",

language = "English",

pages = "43--48",

editor = "W. Zhao and C.A. Moritz",

booktitle = "2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)",

publisher = "Association for Computing Machinery (ACM)",

address = "United States",

note = "2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), NANOARCH 2016 ; Conference date: 18-07-2016 Through 20-07-2016",

}

Du Nguyen, HA, Xie, L, Taouil, M , Hamdioui, S & Bertels, K 2016, Synthesizing HDL to Memristor Technology: A Generic Framework. in W Zhao & CA Moritz (eds), 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). Association for Computing Machinery (ACM), New York, pp. 43-48, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Beijing, China, 18/07/16. https://doi.org/10.1145/2950067.2950098

Synthesizing HDL to Memristor Technology: A Generic Framework. / Du Nguyen, Hoang Anh; Xie, Lei; Taouil, Mottaqiallah et al.
2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). ed. / W. Zhao; C.A. Moritz. New York: Association for Computing Machinery (ACM), 2016. p. 43-48.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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T1 - Synthesizing HDL to Memristor Technology

T2 - 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

AU - Du Nguyen, Hoang Anh

AU - Xie, Lei

AU - Taouil, Mottaqiallah

AU - Hamdioui, Said

AU - Bertels, Koen

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N2 - Memristors are emerging devices with huge potentials. It has been shown that they can be used not only to design non-volatile memories, but also logic circuits. In the latter, memristor devices are stacked on a CMOS circuit whichgenerates the required control signals needed by the memristors to perform the required functionality. This paper sets a step towards automating this process; it proposes a generic synthesis framework to map logic circuits on memristorcrossbar. The framework takes HDL descriptions as input and generates both its memristor circuitry and its associated CMOS control. The framework consists of three phases: (i) netlist generation, (ii) partition and mapping, and (iii) placement and routing. To illustrate the framework, a combinational and a sequential circuit are investigated. The results are validated using HSPICE simulations.

AB - Memristors are emerging devices with huge potentials. It has been shown that they can be used not only to design non-volatile memories, but also logic circuits. In the latter, memristor devices are stacked on a CMOS circuit whichgenerates the required control signals needed by the memristors to perform the required functionality. This paper sets a step towards automating this process; it proposes a generic synthesis framework to map logic circuits on memristorcrossbar. The framework takes HDL descriptions as input and generates both its memristor circuitry and its associated CMOS control. The framework consists of three phases: (i) netlist generation, (ii) partition and mapping, and (iii) placement and routing. To illustrate the framework, a combinational and a sequential circuit are investigated. The results are validated using HSPICE simulations.

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KW - IP networks

KW - Radiation detectors

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ER -

Synthesizing HDL to Memristor Technology: A Generic Framework

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Keywords

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