System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs

K Chandrasekar; C Weis; B Akesson; N Wehn; KGW Goossens

doi:10.7873/DATE.2013.061

System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs

K Chandrasekar, C Weis, B Akesson, N Wehn, KGW Goossens

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

Original language	English
Title of host publication	Proceedings 2013 Design, Automation & Test in Europe conference & exhibition
Editors	K Preas
Place of Publication	Leuven, Belgium
Publisher	EDAA
Pages	236-241
Number of pages	6
ISBN (Print)	978-3-9815370-0-0
DOIs	https://doi.org/10.7873/DATE.2013.061
Publication status	Published - 2013
Event	DATE 2013, Grenoble, France - Leuven, Belgium Duration: 18 Mar 2013 → 22 Mar 2013

Publication series

Name
Publisher	EDAA

Conference

Conference	DATE 2013, Grenoble, France
Period	18/03/13 → 22/03/13

Access to Document

10.7873/DATE.2013.061

Cite this

@inproceedings{33acdece258b4a3c8c0fa7b8cee91d4a,

title = "System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs",

author = "K Chandrasekar and C Weis and B Akesson and N Wehn and KGW Goossens",

year = "2013",

doi = "10.7873/DATE.2013.061",

language = "English",

isbn = "978-3-9815370-0-0",

publisher = "EDAA",

pages = "236--241",

editor = "K Preas",

booktitle = "Proceedings 2013 Design, Automation & Test in Europe conference & exhibition",

note = "DATE 2013, Grenoble, France ; Conference date: 18-03-2013 Through 22-03-2013",

}

System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs. / Chandrasekar, K; Weis, C; Akesson, B et al.
Proceedings 2013 Design, Automation & Test in Europe conference & exhibition. ed. / K Preas. Leuven, Belgium: EDAA, 2013. p. 236-241.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs

AU - Chandrasekar, K

AU - Weis, C

AU - Akesson, B

AU - Wehn, N

AU - Goossens, KGW

PY - 2013

Y1 - 2013

U2 - 10.7873/DATE.2013.061

DO - 10.7873/DATE.2013.061

M3 - Conference contribution

SN - 978-3-9815370-0-0

SP - 236

EP - 241

BT - Proceedings 2013 Design, Automation & Test in Europe conference & exhibition

A2 - Preas, K

PB - EDAA

CY - Leuven, Belgium

T2 - DATE 2013, Grenoble, France

Y2 - 18 March 2013 through 22 March 2013

ER -