System level methodology for interconnect aware and temperature constrained power management of 3D MP-SoCs

SS Kumar, A Aggarwal, R Jagtap, A Zjajo, TGRM van Leuken

Research output: Contribution to journal › Article › Scientific › peer-review

10 Citations (Scopus)

Original language	English
Pages (from-to)	1606-1619
Number of pages	14
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	22
Issue number	7
DOIs	https://doi.org/10.1109/TVLSI.2013.2273003
Publication status	Published - 2014

Available online 24-7-2013

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@article{36fdab85cfdd4550bf057cdb41dd3486,

title = "System level methodology for interconnect aware and temperature constrained power management of 3D MP-SoCs",

author = "SS Kumar and A Aggarwal and R Jagtap and A Zjajo and {van Leuken}, TGRM",

note = "Available online 24-7-2013",

year = "2014",

doi = "10.1109/TVLSI.2013.2273003",

language = "English",

volume = "22",

pages = "1606--1619",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

number = "7",

}

TY - JOUR

T1 - System level methodology for interconnect aware and temperature constrained power management of 3D MP-SoCs

AU - Kumar, SS

AU - Aggarwal, A

AU - Jagtap, R

AU - Zjajo, A

AU - van Leuken, TGRM

N1 - Available online 24-7-2013

PY - 2014

Y1 - 2014

U2 - 10.1109/TVLSI.2013.2273003

DO - 10.1109/TVLSI.2013.2273003

M3 - Article

VL - 22

SP - 1606

EP - 1619

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 7

ER -