System level methodology for interconnect aware and temperature constrained power management of 3D MP-SoCs

SS Kumar, A Aggarwal, R Jagtap, A Zjajo, TGRM van Leuken

Research output: Contribution to journalArticleScientificpeer-review

10 Citations (Scopus)
Original languageEnglish
Pages (from-to)1606-1619
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number7
Publication statusPublished - 2014

Bibliographical note

Available online 24-7-2013

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