Today's computing architectures and device technologies are incapable of meeting the increasingly stringent demands on energy and performance posed by evolving applications. Therefore, alternative novel post-CMOS computing architectures are being explored. One of these is a Computation-in-Memory (CIM) architecture based on memristive devices; it integrates the processing units and the storage in the same physical location (i.e., the memory based on memristive devices). Due to their advanced manufacturing processes, use of new materials, and dual functionality, testing such chips requires specific schemes and therefore special attention. This paper describes the need for testing CIM architectures, proposes a systematic test approach, and shows the strong dependency of the test solutions on the nature of the architecture. All of these will be demonstrated using a design that is designed for computation-in-memory bit-wise logical operations.
|Title of host publication||2019 IEEE International Test Conference (ITC)|
|Number of pages||10|
|Publication status||Published - 9 Nov 2019|
|Event|| ITC 2019: IEEE International Test Conference - Washington, United States|
Duration: 9 Nov 2019 → 15 Nov 2019
|Conference||ITC 2019: IEEE International Test Conference|
|Period||9/11/19 → 15/11/19|