Testing static random access memories - Defects, fault models and test patters

Research output: Book/ReportBookScientific


Embedded memories are one of the fastest growing segments of today's new technology market. According to the 2001 International Technology Roadmap for Semiconductors, embedded memories will continue to dominate the increasing system on chip (SoC) content in the next several years, approaching 94% of the SoC area in about 10 years. Furthermore, the shrinking size of manufacturing structures makes memories more sensitive to defects. Consequently, the memory yield will have a dramatic impact on the overall Defect-per-million level, hence on the overall SoC yield. Meeting a high memory yield requires understanding memory designs, modeling their faulty behaviors, designing adequate tests and diagnosis algorithms as well as efficient self-test and repair schemes. Testing Static Random Access Memories covers testing of one of the important semiconductor memories types; it addresses testing of static random access memories (SRAMs), both single-port and multi-port. It contributes to the technical acknowledge needed by those involved in memory testing, engineers and researchers. The book begins with outlining the most popular SRAMs architectures. Then, the description of realistic fault models, based on defect injection and SPICE simulation, are introduced. Thereafter, high quality and low cost test patterns, as well as test strategies for single-port, two-port and any p-port SRAMs are presented, together with some preliminary test results showing the importance of the new tests in reducing DPM level. The impact of the port restrictions (e.g., read-only ports) on the fault models, tests, and test strategies is also discussed. Features: Fault primitive based analysis of memory faults, A complete framework of and classification memory faults, A systematic way to develop optimal and high quality memory test algorithms, A systematic way to develop test patterns for any multi-port SRAM, Challenges and trends in embedded memory testing.
Original languageUndefined/Unknown
Place of PublicationBoston
PublisherKluwer Academic Publishers
Number of pages240
VolumeFrontiers in electronic testing
ISBN (Print)1-4020-7752-1
Publication statusPublished - 2004

Publication series

PublisherKluwer Academic Publishers


  • authored books
  • Boek internat.wet. > 80 pag

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