Abstract
Many of CMOS SRAMs (like 8T-SRAMs), DRAMs, non-volatile memories and TFET SRAMs use single ended read. Optimization of such sensing schemes is critical. Conventional single ended sensing requires either full discharge of bitline (BL) or voltage/current reference in order to use differential sense amplifier. There is speed and/or power penalty because of either full discharge of BL or complex sense amplifier using references. In this paper, a TFET negative differential resistance property based skewed inverter single-ended read scheme has been proposed. This sensing scheme detects read with less than 200mV BL discharge with inverter based sensing. This results in simplified single ended scheme with speed and BL discharge similar to differential sensing schemes. Less than 400ps read delay is achieved for 200mV BL discharge at 1V supply.
| Original language | English |
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| Title of host publication | 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) |
| Editors | W. Zhao, C.A. Moritz |
| Place of Publication | New York |
| Publisher | Association for Computing Machinery (ACM) |
| Pages | 13-14 |
| Number of pages | 2 |
| ISBN (Electronic) | 978-1-4503-4330-5 |
| ISBN (Print) | 978-1-4673-8927-3 |
| Publication status | Published - 2016 |
| Event | 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - Beijing, China Duration: 18 Jul 2016 → 20 Jul 2016 |
Conference
| Conference | 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) |
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| Abbreviated title | NANOARCH 2016 |
| Country/Territory | China |
| City | Beijing |
| Period | 18/07/16 → 20/07/16 |
Keywords
- TFETs
- Sensors
- Inverters
- Discharges (electric)
- Random access memory
- Power demand
- Delays