TY - GEN
T1 - The DeSyRe project
T2 - 15th Euromicro Conference on Digital System Design, DSD 2012
AU - Sourdis, I.
AU - Strydis, C.
AU - Bouganis, C. S.
AU - Falsafi, B.
AU - Gaydadjiev, G. N.
AU - Malek, A.
AU - Mariani, R.
AU - Pnevmatikatos, D.
AU - Pradhan, D. K.
AU - Rauwerda, G.
AU - Sunesen, K.
AU - Tzilis, S.
PY - 2012
Y1 - 2012
N2 - The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect-/fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe will deliver a new generation of systems that are reliable by design at well-balanced power, performance, and design costs.
AB - The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect-/fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe will deliver a new generation of systems that are reliable by design at well-balanced power, performance, and design costs.
KW - Fault-Tolerance
KW - Medical Systems
KW - Reconfigurable Hardware
KW - System-on-Chip
UR - http://www.scopus.com/inward/record.url?scp=84872972232&partnerID=8YFLogxK
U2 - 10.1109/DSD.2012.127
DO - 10.1109/DSD.2012.127
M3 - Conference contribution
AN - SCOPUS:84872972232
SN - 9780769547985
T3 - Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012
SP - 335
EP - 342
BT - Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012
Y2 - 5 September 2012 through 8 September 2012
ER -