Abstract
In this work, analytical stability equations are derived and combined with a physics-based model of an LDMOS transistor in order to identify the primary cause of failure in different operating and bias conditions. It is found that there is a gradual boundary between an electrical failure region at high drain voltage and a thermal failure region at high junction temperature. The theoretical results are mapped onto a 3D space comprising gate-width normalized drain current, drain voltage and junction temperature, allowing an immediate visualization of the different failure mechanisms. The validity of the proposed analysis is supported by measurements of the safe operating limits of silicon-on-insulator (SOI) LDMOS transistors.
Original language | English |
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Title of host publication | Proceedings of the 2013 IEEE International Electron Devices Meeting |
Place of Publication | Piscataway |
Publisher | IEEE |
Number of pages | 4 |
ISBN (Print) | 978-1-4799-2307-6 |
DOIs | |
Publication status | Published - 2013 |
Event | 2013 IEEE International Electron Devices Meeting - Washington, United States Duration: 9 Dec 2013 → 11 Dec 2013 |
Conference
Conference | 2013 IEEE International Electron Devices Meeting |
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Country/Territory | United States |
City | Washington |
Period | 9/12/13 → 11/12/13 |