The safe operating volume as a general measure for the operating limits of LDMOS transistors

Alessandro Ferrara, Peter Steeneken, Anco Heringa, Boni K. Boksteen, M Swanenberg, AJ Scholten, L van Dijk, Jurriaan Schmitz, Raymond J.E. Hueting

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

1 Citation (Scopus)

Abstract

In this work, analytical stability equations are derived and combined with a physics-based model of an LDMOS transistor in order to identify the primary cause of failure in different operating and bias conditions. It is found that there is a gradual boundary between an electrical failure region at high drain voltage and a thermal failure region at high junction temperature. The theoretical results are mapped onto a 3D space comprising gate-width normalized drain current, drain voltage and junction temperature, allowing an immediate visualization of the different failure mechanisms. The validity of the proposed analysis is supported by measurements of the safe operating limits of silicon-on-insulator (SOI) LDMOS transistors.
Original languageEnglish
Title of host publicationProceedings of the 2013 IEEE International Electron Devices Meeting
Place of PublicationPiscataway
PublisherIEEE
Number of pages4
ISBN (Print)978-1-4799-2307-6
DOIs
Publication statusPublished - 2013
Event2013 IEEE International Electron Devices Meeting - Washington, United States
Duration: 9 Dec 201311 Dec 2013

Conference

Conference2013 IEEE International Electron Devices Meeting
CountryUnited States
CityWashington
Period9/12/1311/12/13

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