The TM3270 media-processor data cache

JW van de Waerdt, S Vassiliadis, JP van Itegem, H van Antwerpen

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

3 Citations (Scopus)


This paper describes the (micro-) architecture of the TM3270 data cache. We present the cache parameters, such as cache size, associativity, line size and cache policies. We describe the data cache pipeline partitioning and the cache memory structure organization. We introduce "collapsed" and "twoslot" load operations. Furthermore, we introduce a combined software/hardware based technique for prefetching of data into the cache. We use an MPEG2 encoder application for a quantative evaluation of architectural aspects such as data prefetching and show that MPEG2 encoding at 352*288 resolution (CIF) at 25 frames per second can be performed in 33.3 MHz.
Original languageUndefined/Unknown
Title of host publicationComputer design: VLSI in computers & processors, IICD 2005
Editors s.n.
Place of PublicationPiscataway
PublisherIEEE Society
Number of pages8
ISBN (Print)0-7695-2451-6
Publication statusPublished - 2005
EventIEEE iInternational conference of computer design (ICCD) 2005, San Jose, USA - Piscataway
Duration: 2 Oct 20055 Oct 2005

Publication series



ConferenceIEEE iInternational conference of computer design (ICCD) 2005, San Jose, USA


  • conference contrib. refereed
  • Conf.proc. > 3 pag

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