This paper describes the (micro-) architecture of the TM3270 data cache. We present the cache parameters, such as cache size, associativity, line size and cache policies. We describe the data cache pipeline partitioning and the cache memory structure organization. We introduce "collapsed" and "twoslot" load operations. Furthermore, we introduce a combined software/hardware based technique for prefetching of data into the cache. We use an MPEG2 encoder application for a quantative evaluation of architectural aspects such as data prefetching and show that MPEG2 encoding at 352*288 resolution (CIF) at 25 frames per second can be performed in 33.3 MHz.
|Conference||IEEE iInternational conference of computer design (ICCD) 2005, San Jose, USA|
|Period||2/10/05 → 5/10/05|
- conference contrib. refereed
- Conf.proc. > 3 pag