TY - GEN
T1 - Thermal-mechanical-electrical Co-design of Fan-Out Panel-Level SiC MOSFET Packaging with a Multi-objective Optimization Algorithm
AU - Chen, Wei
AU - Yan, Xuyang
AU - Ibrahim, Mesfin S.
AU - Meda, Abdulmelik H.
AU - Fan, Xuejun
AU - Zhang, Guoqi
AU - Fan, Jiajie
N1 - Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.
PY - 2023
Y1 - 2023
N2 - As the next generation of semiconductor devices, SiC MOSFETs have demonstrated significant performance improvements in switching loss, switching frequency, and high-temperature operation compared to Si-based MOSFETs. However, the long-term reliability of such devices and their packaging continues to be a major concern. Towards addressing this challenge, this study proposes a multi-objective optimization design method for parasitic inductance (L), thermal strain (?), and thermal resistance (R) of SiC MOSFETs with Fan-Out Panel-Level Packaging (FOPLP). First, the orthogonal experimental design was employed to investigate the thickness effects of baseplate, solder, die and redistribution layer (RDL) on L, e, and R. Then, the multi-objective optimization was developed to simultaneously reduce L, G, and R. Finally the fatigue lifetimes of the optimized and initial SiC MOSFET FOPLP structures were compared to verify the optimization's accuracy. Study findings include: (1) Solder thickness was the most significant influence factor for L, e and R of SiC MOSFET FOPLP, L and R increased, and e decreased with increasing solder thickness; (2) The proposed multi-objective optimization method coupled with a genetic algorithm achieved 14.79, 8.96, and 9.28% reduction of L, e, and R, respectively; (3) The fatigue lifetime of solder (SAC305) was evaluated using the Coffin-Manson model, with predicted lifetimes before and after optimization being 6786 and 7085 cycles, respectively, demonstrating that the proposed approach significantly enhanced the designed SiC MOSFET FOPLP's long-term thermal cycling reliability.
AB - As the next generation of semiconductor devices, SiC MOSFETs have demonstrated significant performance improvements in switching loss, switching frequency, and high-temperature operation compared to Si-based MOSFETs. However, the long-term reliability of such devices and their packaging continues to be a major concern. Towards addressing this challenge, this study proposes a multi-objective optimization design method for parasitic inductance (L), thermal strain (?), and thermal resistance (R) of SiC MOSFETs with Fan-Out Panel-Level Packaging (FOPLP). First, the orthogonal experimental design was employed to investigate the thickness effects of baseplate, solder, die and redistribution layer (RDL) on L, e, and R. Then, the multi-objective optimization was developed to simultaneously reduce L, G, and R. Finally the fatigue lifetimes of the optimized and initial SiC MOSFET FOPLP structures were compared to verify the optimization's accuracy. Study findings include: (1) Solder thickness was the most significant influence factor for L, e and R of SiC MOSFET FOPLP, L and R increased, and e decreased with increasing solder thickness; (2) The proposed multi-objective optimization method coupled with a genetic algorithm achieved 14.79, 8.96, and 9.28% reduction of L, e, and R, respectively; (3) The fatigue lifetime of solder (SAC305) was evaluated using the Coffin-Manson model, with predicted lifetimes before and after optimization being 6786 and 7085 cycles, respectively, demonstrating that the proposed approach significantly enhanced the designed SiC MOSFET FOPLP's long-term thermal cycling reliability.
KW - FOPLP
KW - Genetic algorithms
KW - Orthogonal experimental design
KW - Reliability optimization
KW - SiC MOSFET
UR - http://www.scopus.com/inward/record.url?scp=85168307891&partnerID=8YFLogxK
U2 - 10.1109/ECTC51909.2023.00344
DO - 10.1109/ECTC51909.2023.00344
M3 - Conference contribution
AN - SCOPUS:85168307891
T3 - Proceedings - Electronic Components and Technology Conference
SP - 2007
EP - 2011
BT - Proceedings - IEEE 73rd Electronic Components and Technology Conference, ECTC 2023
PB - IEEE
T2 - 73rd IEEE Electronic Components and Technology Conference, ECTC 2023
Y2 - 30 May 2023 through 2 June 2023
ER -