Abstract
Considerable advancements in power semiconductor devices have resulted in such devices being increasingly adopted in applications of energy generation, conversion, and transmission. Hence, we proposed a fan-out panel-level packaging (FOPLP) design for 30-V Si-based metal-oxide-semiconductor field-effect transistor (MOSFET). To achieve superior reliability of packaging, we applied the nondominated sorting genetic algorithm with elitist strategy (NSGA-II) and ant colony optimization-backpropagation neural network (ACO-BPNN) to optimize the design of redistribution layer (RDL) in FOPLP. We first quantified the thermal resistance and thermomechanical coupling stress of the designed package under thermal cycling loading. Next, NSGA-II and ACO-BPNN were used to optimize the size of the RDL blind via. Finally, the effectiveness of the proposed reliability optimization methods was verified by performing thermal shock reliability aging tests on the prepared devices.
Original language | English |
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Pages (from-to) | 481-488 |
Number of pages | 8 |
Journal | IEEE Transactions on Components, Packaging and Manufacturing Technology |
Volume | 13 |
Issue number | 4 |
DOIs | |
Publication status | Published - 2023 |
Bibliographical note
Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-careOtherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.
Keywords
- Ant Colony Neural Network
- Fan-out panel-level packaging
- Genetic Algorithm
- MOSFET
- Packaging
- Power device
- Reliability
- Reliability optimization
- Stress
- Thermal resistance
- Thermal stresses
- Thermomechanical processes