TLM modelling of 3D stacked wide I/O DRAM Subsystems

M Jung; C Weis; N Wehn; K Chandrasekar

doi:10.1145/2432516.2432521

TLM modelling of 3D stacked wide I/O DRAM Subsystems

M Jung, C Weis, N Wehn, K Chandrasekar

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

Original language	English
Title of host publication	Proceedings 5th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
Editors	G Palermo, D Gracia Perez, J Castrillon et al
Place of Publication	New York, NY, USA
Publisher	Association for Computing Machinery (ACM)
Pages	1-6
Number of pages	6
ISBN (Print)	978-1-4503-1539-5
DOIs	https://doi.org/10.1145/2432516.2432521
Publication status	Published - 2013
Event	RAPIDO 2013, Berlin, Germany - New York, NY, USA Duration: 21 Jan 2013 → 21 Jan 2013

Publication series

Name
Publisher	ACM

Conference

Conference	RAPIDO 2013, Berlin, Germany
Period	21/01/13 → 21/01/13

Access to Document

10.1145/2432516.2432521

Cite this

@inproceedings{5d538083f7ab40fcb858e2768cb8a1b6,

title = "TLM modelling of 3D stacked wide I/O DRAM Subsystems",

author = "M Jung and C Weis and N Wehn and K Chandrasekar",

year = "2013",

doi = "10.1145/2432516.2432521",

language = "English",

isbn = "978-1-4503-1539-5",

publisher = "Association for Computing Machinery (ACM)",

pages = "1--6",

editor = "G Palermo and {Gracia Perez}, D and {Castrillon et al}, J",

booktitle = "Proceedings 5th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools",

address = "United States",

note = "RAPIDO 2013, Berlin, Germany ; Conference date: 21-01-2013 Through 21-01-2013",

}

Jung, M, Weis, C, Wehn, N & Chandrasekar, K 2013, TLM modelling of 3D stacked wide I/O DRAM Subsystems. in G Palermo, D Gracia Perez & J Castrillon et al (eds), Proceedings 5th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools. Association for Computing Machinery (ACM), New York, NY, USA, pp. 1-6, RAPIDO 2013, Berlin, Germany, 21/01/13. https://doi.org/10.1145/2432516.2432521

TLM modelling of 3D stacked wide I/O DRAM Subsystems. / Jung, M; Weis, C; Wehn, N et al.
Proceedings 5th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools. ed. / G Palermo; D Gracia Perez; J Castrillon et al. New York, NY, USA: Association for Computing Machinery (ACM), 2013. p. 1-6.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - TLM modelling of 3D stacked wide I/O DRAM Subsystems

AU - Jung, M

AU - Weis, C

AU - Wehn, N

AU - Chandrasekar, K

PY - 2013

Y1 - 2013

U2 - 10.1145/2432516.2432521

DO - 10.1145/2432516.2432521

M3 - Conference contribution

SN - 978-1-4503-1539-5

SP - 1

EP - 6

BT - Proceedings 5th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

A2 - Palermo, G

A2 - Gracia Perez, D

A2 - Castrillon et al, J

PB - Association for Computing Machinery (ACM)

CY - New York, NY, USA

T2 - RAPIDO 2013, Berlin, Germany

Y2 - 21 January 2013 through 21 January 2013

ER -