Tolerating Retention Failures in Neuromorphic Fabric based on Emerging Resistive Memories

Christopher Münch, Rajendra Bishnoi, Mehdi B. Tahoori

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

7 Citations (Scopus)

Abstract

In recent years, computation is shifting from conventional high performance servers to Internet of Things (IoT) edge devices, most of which require the processing of cognitive tasks. Hence, a great effort is put in the realization of neural network (NN) edge devices and their efficiency in inferring a pretrained Neural Network. In this paper, we evaluate the retention issues of emerging resistive memories used as non-volatile weight storage for embedded NN. We exploit the asymmetric retention behavior of Spintronic based Magnetic Tunneling Junctions (MTJs), which is also present in other resistive memories like Phase-Change memory (PCM) and ReRAM, to optimize the retention of the NN accuracy over time. We propose mixed retention cell arrays and an adapted training scheme to achieve a trade-off between array size and the reliable long-term accuracy of NNs. The results of our proposed method save up to 24% of inference accuracy of an MNIST trained Multi-Layer-Perceptron on MTJ-based crossbars.

Original languageEnglish
Title of host publicationASP-DAC 2020
Subtitle of host publication25th Asia and South Pacific Design Automation Conference, Proceedings
PublisherIEEE
Pages393-400
Number of pages8
ISBN (Electronic)978-1-7281-4123-7
ISBN (Print)978-1-7281-4124-4
DOIs
Publication statusPublished - 2020
Event2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) - Beijing, China
Duration: 13 Jan 202016 Jan 2020
Conference number: 25th

Conference

Conference2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)
Country/TerritoryChina
CityBeijing
Period13/01/2016/01/20

Keywords

  • neural networks
  • resistive memory
  • retention

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