Towards Robust Implementation of Memristor Crossbar Logic Circuits

L. Xie

doi:10.1109/PRIME.2016.7519463

Towards Robust Implementation of Memristor Crossbar Logic Circuits

L. Xie

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

4 Citations (Scopus)

Abstract

Memristor crossbar is a promising technology for future VLSI circuits due to its scalability, non-volatility, high integration density, etc. However, sneak path currents in the crossbar pose major robustness challenges. One proposed solution is applying half-select voltages to floating nanowires (which are not involved in logic operations). This paper analyzes the sneak path issue after applying half-select voltages, and then uses this analysis to derive a set of realization parameter constraints for robustness. In addition, the constraints are used to estimate maximal crossbar size of logic circuits. As a case study, a one-bit full adder is implemented and verified with SPICE simulations; the results show that the proposed approach accurately predicts the impact of sneak path currents with a maximal error of 0.06V.

Original language	English
Title of host publication	2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
Place of Publication	Piscataway., NJ
Publisher	IEEE
Pages	1-4
Number of pages	4
ISBN (Print)	978-1-5090-0493-5
DOIs	https://doi.org/10.1109/PRIME.2016.7519463
Publication status	Published - 2016
Event	PRIME 2016: 12th Conference on PhD Research in Microelectronics and Electronics - Lisbon, Portugal Duration: 27 Jun 2016 → 30 Jun 2016 Conference number: 12

Conference

Conference	PRIME 2016
Country/Territory	Portugal
City	Lisbon
Period	27/06/16 → 30/06/16

Keywords

adders
logic circuits
memristor circuits
nanowires
SPICE simulations
VLSI circuits
floating nanowires
full adder
half-select voltages
logic operations
memristor crossbar logic circuits
realization parameter constraints
robust implementation
sneak path currents
word length 1 bit
Equivalent circuits
Frequency modulation
Memristors
Nanowires
Resistance
Robustness
Switches

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10.1109/PRIME.2016.7519463

Cite this

@inproceedings{af096d435b6b4cc58786896d4b3b4eea,

title = "Towards Robust Implementation of Memristor Crossbar Logic Circuits",

abstract = "Memristor crossbar is a promising technology for future VLSI circuits due to its scalability, non-volatility, high integration density, etc. However, sneak path currents in the crossbar pose major robustness challenges. One proposed solution is applying half-select voltages to floating nanowires (which are not involved in logic operations). This paper analyzes the sneak path issue after applying half-select voltages, and then uses this analysis to derive a set of realization parameter constraints for robustness. In addition, the constraints are used to estimate maximal crossbar size of logic circuits. As a case study, a one-bit full adder is implemented and verified with SPICE simulations; the results show that the proposed approach accurately predicts the impact of sneak path currents with a maximal error of 0.06V.",

keywords = "adders, logic circuits, memristor circuits, nanowires, SPICE simulations, VLSI circuits, floating nanowires, full adder, half-select voltages, logic operations, memristor crossbar logic circuits, realization parameter constraints, robust implementation, sneak path currents, word length 1 bit, Equivalent circuits, Frequency modulation, Memristors, Nanowires, Resistance, Robustness, Switches",

author = "L. Xie",

year = "2016",

doi = "10.1109/PRIME.2016.7519463",

language = "English",

isbn = "978-1-5090-0493-5",

pages = "1--4",

booktitle = "2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)",

publisher = "IEEE",

address = "United States",

note = "PRIME 2016 : 12th Conference on PhD Research in Microelectronics and Electronics ; Conference date: 27-06-2016 Through 30-06-2016",

}

TY - GEN

T1 - Towards Robust Implementation of Memristor Crossbar Logic Circuits

AU - Xie, L.

N1 - Conference code: 12

PY - 2016

Y1 - 2016

N2 - Memristor crossbar is a promising technology for future VLSI circuits due to its scalability, non-volatility, high integration density, etc. However, sneak path currents in the crossbar pose major robustness challenges. One proposed solution is applying half-select voltages to floating nanowires (which are not involved in logic operations). This paper analyzes the sneak path issue after applying half-select voltages, and then uses this analysis to derive a set of realization parameter constraints for robustness. In addition, the constraints are used to estimate maximal crossbar size of logic circuits. As a case study, a one-bit full adder is implemented and verified with SPICE simulations; the results show that the proposed approach accurately predicts the impact of sneak path currents with a maximal error of 0.06V.

AB - Memristor crossbar is a promising technology for future VLSI circuits due to its scalability, non-volatility, high integration density, etc. However, sneak path currents in the crossbar pose major robustness challenges. One proposed solution is applying half-select voltages to floating nanowires (which are not involved in logic operations). This paper analyzes the sneak path issue after applying half-select voltages, and then uses this analysis to derive a set of realization parameter constraints for robustness. In addition, the constraints are used to estimate maximal crossbar size of logic circuits. As a case study, a one-bit full adder is implemented and verified with SPICE simulations; the results show that the proposed approach accurately predicts the impact of sneak path currents with a maximal error of 0.06V.

KW - adders

KW - logic circuits

KW - memristor circuits

KW - nanowires

KW - SPICE simulations

KW - VLSI circuits

KW - floating nanowires

KW - full adder

KW - half-select voltages

KW - logic operations

KW - memristor crossbar logic circuits

KW - realization parameter constraints

KW - robust implementation

KW - sneak path currents

KW - word length 1 bit

KW - Equivalent circuits

KW - Frequency modulation

KW - Memristors

KW - Nanowires

KW - Resistance

KW - Robustness

KW - Switches

U2 - 10.1109/PRIME.2016.7519463

DO - 10.1109/PRIME.2016.7519463

M3 - Conference contribution

SN - 978-1-5090-0493-5

SP - 1

EP - 4

BT - 2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

PB - IEEE

CY - Piscataway., NJ

T2 - PRIME 2016

Y2 - 27 June 2016 through 30 June 2016

ER -

Towards Robust Implementation of Memristor Crossbar Logic Circuits

Abstract

Conference

Keywords

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