Transistor-level gate model based statistical timing analysis considering correlations

Q Tang; A Zjajo; MRCM Berkelaar; NP van der Meijs

doi:10.1109/DATE.2012.6176628

Transistor-level gate model based statistical timing analysis considering correlations

Q Tang, A Zjajo, MRCM Berkelaar, NP van der Meijs

Signal Processing Systems

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

7 Citations (Scopus)

Original language	English
Title of host publication	Proceedings of the 2012 Design, Automation & Test in Europe Conference and Exhibition
Editors	L Thiele, EJ Marinissen et al
Place of Publication	Piscataway, USA
Publisher	IEEE
Pages	917-922
Number of pages	6
ISBN (Print)	978-3-9810801-8-6
DOIs	https://doi.org/10.1109/DATE.2012.6176628
Publication status	Published - 2012
Event	DATE2012, Dresden, Germany - Piscataway, USA Duration: 12 Mar 2012 → 16 Mar 2012

Publication series

Name
Publisher	IEEE

Conference

Conference	DATE2012, Dresden, Germany
Period	12/03/12 → 16/03/12

Access to Document

10.1109/DATE.2012.6176628

Cite this

@inproceedings{5466c30cd15144bc990cab4a61842c4c,

title = "Transistor-level gate model based statistical timing analysis considering correlations",

author = "Q Tang and A Zjajo and MRCM Berkelaar and {van der Meijs}, NP",

year = "2012",

doi = "10.1109/DATE.2012.6176628",

language = "English",

isbn = "978-3-9810801-8-6",

publisher = "IEEE",

pages = "917--922",

editor = "L Thiele and {Marinissen et al}, EJ",

booktitle = "Proceedings of the 2012 Design, Automation & Test in Europe Conference and Exhibition",

address = "United States",

note = "DATE2012, Dresden, Germany ; Conference date: 12-03-2012 Through 16-03-2012",

}

Tang, Q, Zjajo, A, Berkelaar, MRCM & van der Meijs, NP 2012, Transistor-level gate model based statistical timing analysis considering correlations. in L Thiele & EJ Marinissen et al (eds), Proceedings of the 2012 Design, Automation & Test in Europe Conference and Exhibition. IEEE, Piscataway, USA, pp. 917-922, DATE2012, Dresden, Germany, 12/03/12. https://doi.org/10.1109/DATE.2012.6176628

Transistor-level gate model based statistical timing analysis considering correlations. / Tang, Q; Zjajo, A; Berkelaar, MRCM et al.
Proceedings of the 2012 Design, Automation & Test in Europe Conference and Exhibition. ed. / L Thiele; EJ Marinissen et al. Piscataway, USA: IEEE, 2012. p. 917-922.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Transistor-level gate model based statistical timing analysis considering correlations

AU - Tang, Q

AU - Zjajo, A

AU - Berkelaar, MRCM

AU - van der Meijs, NP

PY - 2012

Y1 - 2012

U2 - 10.1109/DATE.2012.6176628

DO - 10.1109/DATE.2012.6176628

M3 - Conference contribution

SN - 978-3-9810801-8-6

SP - 917

EP - 922

BT - Proceedings of the 2012 Design, Automation & Test in Europe Conference and Exhibition

A2 - Thiele, L

A2 - Marinissen et al, EJ

PB - IEEE

CY - Piscataway, USA

T2 - DATE2012, Dresden, Germany

Y2 - 12 March 2012 through 16 March 2012

ER -