Transistor-level gate modeling for Nano CMOS circuit verification considering statistical process variations

Q Tang, A Zjajo, MRCM Berkelaar, NP van der Meijs

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Original languageEnglish
Title of host publicationIntegrated Circuit and System Design. Power and Timing Modeling, Optimization ans Simulation
EditorsR van Leuken, G Sicard
Place of PublicationBerlin, Heidelberg
PublisherSpringer
Pages1-10
Number of pages10
ISBN (Print)978-3-642-17751-4
Publication statusPublished - 2010
Event20th International workshop on power and timing modeling, optimization and simulation (PATMOS), Grenoble, France - Berlin, Heidelberg
Duration: 7 Sep 201010 Sep 2010

Publication series

Name
PublisherSpringer Verlag
NameLecture Notes in Computer Science
Volume6448
ISSN (Print)0302-9743

Conference

Conference20th International workshop on power and timing modeling, optimization and simulation (PATMOS), Grenoble, France
Period7/09/1010/09/10

Keywords

  • CWTS JFIS < 0.75

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