Transistor-level gate modeling for Nano CMOS circuit verification considering statistical process variations

Q Tang; A Zjajo; MRCM Berkelaar; NP van der Meijs

Transistor-level gate modeling for Nano CMOS circuit verification considering statistical process variations

Q Tang, A Zjajo, MRCM Berkelaar, NP van der Meijs

Signal Processing Systems

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

Original language	English
Title of host publication	Integrated Circuit and System Design. Power and Timing Modeling, Optimization ans Simulation
Editors	R van Leuken, G Sicard
Place of Publication	Berlin, Heidelberg
Publisher	Springer
Pages	1-10
Number of pages	10
ISBN (Print)	978-3-642-17751-4
Publication status	Published - 2010
Event	20th International workshop on power and timing modeling, optimization and simulation (PATMOS), Grenoble, France - Berlin, Heidelberg Duration: 7 Sept 2010 → 10 Sept 2010

Publication series

Name
Publisher	Springer Verlag

Name	Lecture Notes in Computer Science
Volume	6448
ISSN (Print)	0302-9743

Conference

Conference	20th International workshop on power and timing modeling, optimization and simulation (PATMOS), Grenoble, France
Period	7/09/10 → 10/09/10

Keywords

CWTS JFIS < 0.75

Cite this

Tang, Q., Zjajo, A., Berkelaar, MRCM., & van der Meijs, NP. (2010). Transistor-level gate modeling for Nano CMOS circuit verification considering statistical process variations. In R. van Leuken, & G. Sicard (Eds.), Integrated Circuit and System Design. Power and Timing Modeling, Optimization ans Simulation (pp. 1-10). (Lecture Notes in Computer Science; Vol. 6448). Springer.

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title = "Transistor-level gate modeling for Nano CMOS circuit verification considering statistical process variations",

keywords = "CWTS JFIS < 0.75",

author = "Q Tang and A Zjajo and MRCM Berkelaar and {van der Meijs}, NP",

year = "2010",

language = "English",

isbn = "978-3-642-17751-4",

publisher = "Springer",

pages = "1--10",

editor = "{van Leuken}, R and G Sicard",

booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization ans Simulation",

note = "20th International workshop on power and timing modeling, optimization and simulation (PATMOS), Grenoble, France ; Conference date: 07-09-2010 Through 10-09-2010",

}

Tang, Q, Zjajo, A, Berkelaar, MRCM & van der Meijs, NP 2010, Transistor-level gate modeling for Nano CMOS circuit verification considering statistical process variations. in R van Leuken & G Sicard (eds), Integrated Circuit and System Design. Power and Timing Modeling, Optimization ans Simulation. Lecture Notes in Computer Science, vol. 6448, Springer, Berlin, Heidelberg, pp. 1-10, 20th International workshop on power and timing modeling, optimization and simulation (PATMOS), Grenoble, France, 7/09/10.

Transistor-level gate modeling for Nano CMOS circuit verification considering statistical process variations. / Tang, Q; Zjajo, A; Berkelaar, MRCM et al.
Integrated Circuit and System Design. Power and Timing Modeling, Optimization ans Simulation. ed. / R van Leuken; G Sicard. Berlin, Heidelberg: Springer, 2010. p. 1-10 (Lecture Notes in Computer Science; Vol. 6448).

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Transistor-level gate modeling for Nano CMOS circuit verification considering statistical process variations

AU - Tang, Q

AU - Zjajo, A

AU - Berkelaar, MRCM

AU - van der Meijs, NP

PY - 2010

Y1 - 2010

KW - CWTS JFIS < 0.75

UR - http://ens.ewi.tudelft.nl/pubs/qin2010patmos.pdf

M3 - Conference contribution

SN - 978-3-642-17751-4

SP - 1

EP - 10

BT - Integrated Circuit and System Design. Power and Timing Modeling, Optimization ans Simulation

A2 - van Leuken, R

A2 - Sicard, G

PB - Springer

CY - Berlin, Heidelberg

T2 - 20th International workshop on power and timing modeling, optimization and simulation (PATMOS), Grenoble, France

Y2 - 7 September 2010 through 10 September 2010

ER -

Tang Q, Zjajo A, Berkelaar MRCM, van der Meijs NP. Transistor-level gate modeling for Nano CMOS circuit verification considering statistical process variations. In van Leuken R, Sicard G, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization ans Simulation. Berlin, Heidelberg: Springer. 2010. p. 1-10. (Lecture Notes in Computer Science).

Transistor-level gate modeling for Nano CMOS circuit verification considering statistical process variations

Publication series

Conference

Keywords

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Cite this