Ultra-low phase noise ADPLL for millimeter wave

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review


Millimeter-wave (mm-wave) frequency synthesizers in complementary metal oxide-semiconductor (CMOS) suffer from poor phase noise (PN), limited tuning range (TR) and high-power consumption. They are the key subsystems that typically limit the performance of mm-wave transceivers. This chapter presents a new architecture for mm-wave frequency synthesis that improves its PN performance and power efficiency. Various different techniques are introduced and demonstrated in a 60-GHz fractional-N all-digital phase-locked loop (ADPLL).

Original languageEnglish
Title of host publicationPhase-Locked Frequency Generation and Clocking
PublisherInstitution of Engineering and Technology
Number of pages32
ISBN (Electronic)9781785618857
Publication statusPublished - 2020


  • Cmos digital integrated circuits
  • Digital phase locked loops
  • Field effect mimic
  • Phase noise
  • Power consumption
  • Radio transceivers

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