Ultra-low phase noise ADPLL for millimeter wave

Zhirui Zong; Robert Bogdan Staszewski

doi:10.1049/PBCS064E_ch13

Ultra-low phase noise ADPLL for millimeter wave

Zhirui Zong, Robert Bogdan Staszewski

Electronics

Research output: Chapter in Book/Conference proceedings/Edited volume › Chapter › Scientific › peer-review

Abstract

Millimeter-wave (mm-wave) frequency synthesizers in complementary metal oxide-semiconductor (CMOS) suffer from poor phase noise (PN), limited tuning range (TR) and high-power consumption. They are the key subsystems that typically limit the performance of mm-wave transceivers. This chapter presents a new architecture for mm-wave frequency synthesis that improves its PN performance and power efficiency. Various different techniques are introduced and demonstrated in a 60-GHz fractional-N all-digital phase-locked loop (ADPLL).

Original language	English
Title of host publication	Phase-Locked Frequency Generation and Clocking
Publisher	Institution of Engineering and Technology
Pages	347-378
Number of pages	32
ISBN (Electronic)	9781785618857
DOIs	https://doi.org/10.1049/PBCS064E_ch13
Publication status	Published - 2020

Keywords

Cmos digital integrated circuits
Digital phase locked loops
Field effect mimic
Phase noise
Power consumption
Radio transceivers

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10.1049/PBCS064E_ch13

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abstract = "Millimeter-wave (mm-wave) frequency synthesizers in complementary metal oxide-semiconductor (CMOS) suffer from poor phase noise (PN), limited tuning range (TR) and high-power consumption. They are the key subsystems that typically limit the performance of mm-wave transceivers. This chapter presents a new architecture for mm-wave frequency synthesis that improves its PN performance and power efficiency. Various different techniques are introduced and demonstrated in a 60-GHz fractional-N all-digital phase-locked loop (ADPLL).",

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AB - Millimeter-wave (mm-wave) frequency synthesizers in complementary metal oxide-semiconductor (CMOS) suffer from poor phase noise (PN), limited tuning range (TR) and high-power consumption. They are the key subsystems that typically limit the performance of mm-wave transceivers. This chapter presents a new architecture for mm-wave frequency synthesis that improves its PN performance and power efficiency. Various different techniques are introduced and demonstrated in a 60-GHz fractional-N all-digital phase-locked loop (ADPLL).

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KW - Digital phase locked loops

KW - Field effect mimic

KW - Phase noise

KW - Power consumption

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ER -

Ultra-low phase noise ADPLL for millimeter wave

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Keywords

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