Unbalanced Bit-slicing Scheme for Accurate Memristor-based Neural Network Architecture

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Abstract

Emerging memristor-based computing has the potential to achieve higher computational efficiency over conventional architectures. Bit-slicing scheme, which represents a single neural weight using multiple memristive devices, is usually introduced in memristor-based neural networks to meet high bit-precision demands. However, the accuracy of such networks can be significantly degraded due to non-zero minimum conductance $(\mathrm{G}_{min})$ of memristive devices. This paper proposes an unbalanced bit-slicing scheme; it uses smaller slice sizes for more important bits to provide higher sensing margin and reduces the impact of non-zero $\mathrm{G}_{min}$. Moreover, the unbalanced bit-slicing is assisted by 2’s complement arithmetic which further improves the accuracy. Simulation results show that our proposed scheme can achieve up to $8.8 \times $ and $1.8 \times $ accuracy compared to state-of-the-art for single-bit and two-bit configurations respectively, at reasonable energy overheads.
Original languageEnglish
Title of host publication2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS)
PublisherIEEE
Pages1-4
Number of pages4
ISBN (Electronic)978-1-6654-1913-0
ISBN (Print)978-1-6654-3025-8
DOIs
Publication statusPublished - 2021
Event 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS) - Online at Washington, United States
Duration: 6 Jun 20219 Jun 2021
Conference number: 3rd

Conference

Conference 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS)
CountryUnited States
CityOnline at Washington
Period6/06/219/06/21

Bibliographical note

Accepted author manuscript

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