Vertical silicon-on-nothing FET: threshold voltage calculation using compact capacitance model

B Svilicic, V Jovanovic, T Suligoj

Research output: Contribution to journal › Article › Scientific › peer-review

Keywords

@article{48b98e8146b54e019dea3d7e77617950,

title = "Vertical silicon-on-nothing FET: threshold voltage calculation using compact capacitance model",

keywords = "academic journal papers, CWTS JFIS < 0.75",

author = "B Svilicic and V Jovanovic and T Suligoj",

year = "2008",

language = "Undefined/Unknown",

volume = "52",

pages = "1505--1511",

journal = "Solid-State Electronics",

issn = "0038-1101",

publisher = "Elsevier",

number = "10",

}