Vertical silicon-on-nothing FET: threshold voltage calculation using compact capacitance model

B Svilicic, V Jovanovic, T Suligoj

    Research output: Contribution to journalArticleScientificpeer-review

    8 Citations (Scopus)
    Original languageUndefined/Unknown
    Pages (from-to)1505-1511
    Number of pages7
    JournalSolid-State Electronics
    Volume52
    Issue number10
    Publication statusPublished - 2008

    Keywords

    • academic journal papers
    • CWTS JFIS < 0.75

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