Very low temperature epitaxy of group-IV semiconductors for use in FinFET, stacked nanowires and monolithic 3D integration

C. Porret, A. Hikavyy, J. F. Gomez Granados, S. Baudot, A. Vohra, B. Kunert, B. Douhard, J. Bogdanowicz, A. Sammak, G. Scappucci, E. Rosseel, More Authors

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

6 Citations (Scopus)

Abstract

As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.

Original languageEnglish
Title of host publicationECS Transactions
Editors J.-M. Hartmann, A. Thean , A. Ogura , X. Gong , D. Harame , M. Caymax, G Niu , A. Schulze , Q. Liu , G Mashi, S. Miyazaki , A. Mai, M. Osting
PublisherThe Electrochemical Society, Inc.
Pages163-175
Volume86
Edition7
ISBN (Electronic)978-160768539-5
DOIs
Publication statusPublished - 2018
Event8th Symposium on SiGe, Ge, and Related Compounds: Materials, Processing, and Devices - AiMES 2018, ECS and SMEQ Joint International Meeting - Cancun, Mexico
Duration: 30 Sep 20184 Oct 2018

Conference

Conference8th Symposium on SiGe, Ge, and Related Compounds: Materials, Processing, and Devices - AiMES 2018, ECS and SMEQ Joint International Meeting
CountryMexico
CityCancun
Period30/09/184/10/18

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