Very low temperature epitaxy of group-IV semiconductors for use in FinFET, stacked nanowires and monolithic 3D integration

C. Porret, A. Hikavyy, J. F.Gomez Granados, S. Baudot, A. Vohra, B. Kunert, B. Douhard, A. Sammak, G. Scappucci, More Authors

Research output: Contribution to journalArticleScientificpeer-review

2 Citations (Scopus)
53 Downloads (Pure)

Abstract

As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.

Original languageEnglish
Pages (from-to)P392-P399
JournalECS Journal of Solid State Science and Technology
Volume8
Issue number8
DOIs
Publication statusPublished - 2019

Keywords

  • Microelectronics - Semiconductor Materials
  • Low Temperature Epitaxy
  • Source/Drain materials
  • Strained Channels

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