Very low temperature epitaxy of group-IV semiconductors for use in FinFET, stacked nanowires and monolithic 3D integration

C. Porret; A. Hikavyy; J. F.Gomez Granados; S. Baudot; A. Vohra; B. Kunert; B. Douhard; A. Sammak; G. Scappucci; null More Authors

doi:10.1149/2.0071908jss

Very low temperature epitaxy of group-IV semiconductors for use in FinFET, stacked nanowires and monolithic 3D integration

C. Porret^*, A. Hikavyy, J. F.Gomez Granados, S. Baudot, A. Vohra, B. Kunert, B. Douhard, A. Sammak, G. Scappucci, More Authors

^*Corresponding author for this work

Research output: Contribution to journal › Article › Scientific › peer-review

19 Citations (Scopus)

315 Downloads (Pure)

Abstract

As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.

Original language	English
Pages (from-to)	P392-P399
Journal	ECS Journal of Solid State Science and Technology
Volume	8
Issue number	8
DOIs	https://doi.org/10.1149/2.0071908jss
Publication status	Published - 2019

Keywords

Microelectronics - Semiconductor Materials
Low Temperature Epitaxy
Source/Drain materials
Strained Channels

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10.1149/2.0071908jss

ECS J. Solid State Sci. Technol.-2019-Porret-P392-9Final published version, 1.03 MBLicence: CC BY

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Porret, C., Hikavyy, A., Granados, J. F. G., Baudot, S., Vohra, A., Kunert, B., Douhard, B., Sammak, A., Scappucci, G., & More Authors (2019). Very low temperature epitaxy of group-IV semiconductors for use in FinFET, stacked nanowires and monolithic 3D integration. ECS Journal of Solid State Science and Technology, 8(8), P392-P399. https://doi.org/10.1149/2.0071908jss

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Porret, C, Hikavyy, A, Granados, JFG, Baudot, S, Vohra, A, Kunert, B, Douhard, B, Sammak, A , Scappucci, G & More Authors 2019, 'Very low temperature epitaxy of group-IV semiconductors for use in FinFET, stacked nanowires and monolithic 3D integration', ECS Journal of Solid State Science and Technology, vol. 8, no. 8, pp. P392-P399. https://doi.org/10.1149/2.0071908jss

TY - JOUR

T1 - Very low temperature epitaxy of group-IV semiconductors for use in FinFET, stacked nanowires and monolithic 3D integration

AU - Porret, C.

AU - Hikavyy, A.

AU - Granados, J. F.Gomez

AU - Baudot, S.

AU - Vohra, A.

AU - Kunert, B.

AU - Douhard, B.

AU - Sammak, A.

AU - Scappucci, G.

AU - More Authors, null

PY - 2019

Y1 - 2019

N2 - As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.

AB - As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.

KW - Microelectronics - Semiconductor Materials

KW - Low Temperature Epitaxy

KW - Source/Drain materials

KW - Strained Channels

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DO - 10.1149/2.0071908jss

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VL - 8

SP - P392-P399

JO - ECS Journal of Solid State Science and Technology

JF - ECS Journal of Solid State Science and Technology

IS - 8

ER -

Very low temperature epitaxy of group-IV semiconductors for use in FinFET, stacked nanowires and monolithic 3D integration

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Keywords

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