Virtual Prototyping for PPM-level Failures in Microelectronic Packages

In this paper, the interaction between chip and package is investigated with the focus on low ppm-level failures. More specifically, the failure mode of inter-metal shorts is investigated, caused by either electrical discharges (ESD) or internal/external mechanical forces. It is demonstrated that forces induced by the filler particles in the molding compound can cause these shorts. Finite element simulations are performed in order to estimate the stress levels in the backend stack of the integrated circuit (IC). Nano-indentation experiments are performed to measure the hardness of different passivation materials. The simulation and indentation results are combined with estimations and measurements of the particle size distribution, flow modeling and statistical methods. As such, the ppm-level of the failures could be attributed to the low chance that a filler particle would land on the critical location. Measures to prevent these failures are to be found in the area of improved passivation materials and/or recipes in combination with other molding compounds. For succesful development of IC backend structures and processes, it is essential to take into account the influence of the package in the earlier phase of IC backend development.