VLIW-Based FPGA Computation Fabric with Streaming Memory Hierarchy for Medical Imaging Applications

Joost Hoozemans, R. Heij, Jeroen van Straten, Zaid Al-Ars

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

3 Citations (Scopus)


In this paper, we present and evaluate an FPGA acceleration fabric that uses VLIW softcores as processing elements, combined with a
memory hierarchy that is designed to stream data between intermediate stages of an image processing pipeline. These pipelines are commonplace in medical applications such as X-ray imagers. By using a streaming memory hierarchy, performance is increased by a factor that depends on the number of stages (7.5× when using 4 consecutive filters). Using a Xilinx VC707 board, we are able to place up to 75 cores. A platform of 64 cores can be routed at 193 MHz, achieving real-time performance, while keeping 20% resources available for off-board interfacing. Our VHDL implementation and associated tools (compiler, simulator, etc.) are available for download for the academic community.
Original languageEnglish
Title of host publicationApplied Reconfigurable Computing
Subtitle of host publication13th International Symposium, ARC 2017
EditorsS. Wong, A.C. Beck, K. Bertels, L. Carro
Place of PublicationCham
Number of pages8
ISBN (Electronic)978-3-319-56258-2
ISBN (Print)978-3-319-56257-5
Publication statusPublished - 2017
EventARC 2017: Applied Reconfigurable Computing: 13th International Symposium on Applied Reconfigurable Computing - Delft, Netherlands
Duration: 3 Apr 20177 Apr 2017

Publication series

NameLecture Notes in Computer Science
ISSN (Print)0302-9743
NameTheoretical Computer Science and General Issues
Volume 10216


ConferenceARC 2017: Applied Reconfigurable Computing


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