Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnects at test access mechanism

A Amory, KGW Goossens, E Marinissen, M Lubaszewski, F Moraes

Research output: Contribution to journal › Article › Scientific › peer-review

Original language	Undefined/Unknown
Pages (from-to)	197-206
Number of pages	10
Journal	IET Computers and Digital Techniques
Volume	1
Issue number	3
Publication status	Published - 2007

Keywords

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title = "Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnects at test access mechanism",

keywords = "academic journal papers, CWTS JFIS < 0.75",

author = "A Amory and KGW Goossens and E Marinissen and M Lubaszewski and F Moraes",

note = "NEO",

year = "2007",

language = "Undefined/Unknown",

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pages = "197--206",

journal = "IET Computers and Digital Techniques",

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publisher = "Institution of Engineering and Technology",

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TY - JOUR

T1 - Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnects at test access mechanism

AU - Amory, A

AU - Goossens, KGW

AU - Marinissen, E

AU - Lubaszewski, M

AU - Moraes, F

N1 - NEO

PY - 2007

Y1 - 2007

KW - academic journal papers

KW - CWTS JFIS < 0.75

M3 - Article

VL - 1

SP - 197

EP - 206

JO - IET Computers and Digital Techniques

JF - IET Computers and Digital Techniques

SN - 1751-8601

IS - 3

ER -