Yield improvement and test cost optimization for 3D stacked ICs

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

Original language	English
Title of host publication	20th IEEE Asian Test Symposium 2011
Editors	A Chatterjee, A Patra, S Kundu, S Ravi
Place of Publication	Piscataway, NJ, USA
Publisher	IEEE
Pages	480-485
Number of pages	6
ISBN (Print)	978-0-7695-4583-7
DOIs	https://doi.org/10.1109/ATS.2011.66
Publication status	Published - 2011
Event	ATS 2011 - Piscataway, NJ, USA Duration: 20 Nov 2011 → 23 Nov 2011

Name
Publisher	IEEE

Conference	ATS 2011
Period	20/11/11 → 23/11/11

Access to Document

@inproceedings{9abcbf5ad1454fa190d7837a859c1363,

title = "Yield improvement and test cost optimization for 3D stacked ICs",

author = "S Hamdioui and M Taouil",

year = "2011",

doi = "10.1109/ATS.2011.66",

language = "English",

isbn = "978-0-7695-4583-7",

publisher = "IEEE",

pages = "480--485",

editor = "A Chatterjee and A Patra and S Kundu and S Ravi",

booktitle = "20th IEEE Asian Test Symposium 2011",

address = "United States",

note = "ATS 2011 ; Conference date: 20-11-2011 Through 23-11-2011",

}

TY - GEN

T1 - Yield improvement and test cost optimization for 3D stacked ICs

AU - Hamdioui, S

AU - Taouil, M

PY - 2011

Y1 - 2011

U2 - 10.1109/ATS.2011.66

DO - 10.1109/ATS.2011.66

M3 - Conference contribution

SN - 978-0-7695-4583-7

SP - 480

EP - 485

BT - 20th IEEE Asian Test Symposium 2011

A2 - Chatterjee, A

A2 - Patra, A

A2 - Kundu, S

A2 - Ravi, S

PB - IEEE

CY - Piscataway, NJ, USA

T2 - ATS 2011

Y2 - 20 November 2011 through 23 November 2011

ER -