Cryogenic CMOS Characterization for Quantum Computer Applications

Device characteristics at cryogenic temperatures can deviate significantly from their room temperature behaviour. For example, the threshold voltage of a MOSFET can increase by more than 100 mV when it is cooled down to 4.2 K, as shown in this thesis. If a designer is not aware of this shift, circuits that work as intended at room temperature can potentially fail at deep-cryogenic temperatures due to the resulting change in bias points, or even due to devices that are unable to be switched on.

Device characterization is an indispensable step in building models for circuit designers. Foundries characterize their technology over the standard military temperature range (-55 to 125 ◦C) and generally do not supply compact models (yet) that are valid at deep-cryogenic temperatures. Therefore, designers of cryogenic circuits have to rely on back-of-the-envelope calculations and must build in margins to allow for parameter shifts, as they are unable to fully simulate their designs with use of the existing electrical simulators. These margins cause circuits to most likely occupy more silicon area than required and thus operate at lower speeds and with increased power dissipation compared to an optimized circuit. As the power budget is severely limited, this is a very important challenge of (current) cryogenic circuit design. Worst of all, circuits deviating from the stringent specifications for quantum control can lead to lower fidelity of quantum operations.

In order to overcome these challenges, cryogenic device characterization needs to be carried out, to investigate and capture the impact of low temperatures on different device parameters. A convenient temperature to operate cryogenic circuits at, is that of liquid helium, which lies around 4.2 K. Therefore, most characterizations are carried-out at this temperature.
Effort was already devoted to characterization and modeling at these temperatures by other groups, however, not much attention was spent on the impact of these extreme temperatures on device matching and self-heating in advanced processes.
The work presented in this thesis, therefore, focuses on the design and characterization of test chips in an advanced 40-nm process, and the subsequent modeling of device mismatch and self-heating at cryogenic temperatures.