A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter with Digital Calibration

Ping Lu, Ying Wu, Pietro Andreani

Research output: Contribution to journalArticleScientificpeer-review

18 Citations (Scopus)

Abstract

This brief presents a two-dimensional (2-D) Vernier time-to-digital converter (TDC) which uses two 3-stage gated ring oscillators (GROs) in the X/Y Vernier branches. The already small Vernier quantization noise (∼10.6 ps) is improved by the first-order noise shaping of the GRO. Moreover, since all the delay differences between the X and Y phases can be used (rather than only the diagonal line of the one-dimensional architecture), the intrinsic large latency time of the Vernier architecture is dramatically reduced. The TDC is implemented in a 65-nm CMOS process and consumes 2.3 mA from 1.0 V. The measured total noise integrated over a bandwidth of 1.25 MHz yields an equivalent TDC resolution of 2.2 ps, whereas the average latency time (within 2 ns) is less than 1/6 of that in a standard Vernier TDC.

Original languageEnglish
Article number7442784
Pages (from-to)1019-1023
Number of pages5
JournalIEEE Transactions on Circuits and Systems Part 2: Express Briefs
Volume63
Issue number11
DOIs
Publication statusPublished - 2016

Keywords

  • Gated ring oscillator (GRO)
  • time-to-digital converter (TDC)
  • two-dimensional (2-D)
  • Vernier

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