A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation

Zhong Gao; Martin Fritz; Jingchu He; Gerd Spalink; Robert Bogdan Staszewski; Morteza S. Alavi; Masoud Babaie

doi:10.1109/VLSITechnologyandCir46769.2022.9830398

A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation

Zhong Gao, Martin Fritz, Jingchu He, Gerd Spalink, Robert Bogdan Staszewski, Morteza S. Alavi, Masoud Babaie

Electronics

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

3 Citations (Scopus)

31 Downloads (Pure)

Abstract

We present a broadband digital PLL (DPLL)-based phase modulator supporting wide frequency modulation (FM) bandwidth (BW). It compensates for the EVM degradation due to the non-uniform period of the retimed updating clock and shortens the nonlinearity calibration time of the digitally controlled oscillator (DCO) with a phase-domain digital pre-distortion (DPD) and an encoding-assisted (EA)-LMS calibration. While generating a 10MHz 64-PSK signal, the prototype can achieve -46dB EVM with less than one-tenth of the calibration samples (time) required by the prior art.

Original language	English
Title of host publication	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Publisher	IEEE
Pages	14-15
Number of pages	2
ISBN (Electronic)	9781665497725
DOIs	https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830398
Publication status	Published - 2022
Event	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States Duration: 12 Jun 2022 → 17 Jun 2022

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2022-June
ISSN (Print)	0743-1562

Conference

Conference	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Country/Territory	United States
City	Honolulu
Period	12/06/22 → 17/06/22

Bibliographical note

Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care
Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Access to Document

10.1109/VLSITechnologyandCir46769.2022.9830398

A_DPLL-Based_Phase_Modulator_Achieving_-46dB_EVM_with_A_Fast_Two-Step_DCO_Nonlinearity_Calibration_and_Non-Uniform_Clock_CompensationFinal published version, 1.72 MB

Cite this

Gao, Z., Fritz, M., He, J., Spalink, G., Staszewski, R. B., Alavi, M. S., & Babaie, M. (2022). A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation. In 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 (pp. 14-15). (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2022-June). IEEE. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830398

@inproceedings{febaf40dbf50448b931cce3503c309c4,

title = "A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation",

abstract = "We present a broadband digital PLL (DPLL)-based phase modulator supporting wide frequency modulation (FM) bandwidth (BW). It compensates for the EVM degradation due to the non-uniform period of the retimed updating clock and shortens the nonlinearity calibration time of the digitally controlled oscillator (DCO) with a phase-domain digital pre-distortion (DPD) and an encoding-assisted (EA)-LMS calibration. While generating a 10MHz 64-PSK signal, the prototype can achieve -46dB EVM with less than one-tenth of the calibration samples (time) required by the prior art. ",

author = "Zhong Gao and Martin Fritz and Jingchu He and Gerd Spalink and Staszewski, {Robert Bogdan} and Alavi, {Morteza S.} and Masoud Babaie",

note = "Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.; 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 ; Conference date: 12-06-2022 Through 17-06-2022",

year = "2022",

doi = "10.1109/VLSITechnologyandCir46769.2022.9830398",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "IEEE",

pages = "14--15",

booktitle = "2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022",

address = "United States",

}

Gao, Z, Fritz, M, He, J, Spalink, G, Staszewski, RB , Alavi, MS & Babaie, M 2022, A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation. in 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Digest of Technical Papers - Symposium on VLSI Technology, vol. 2022-June, IEEE, pp. 14-15, 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022, Honolulu, United States, 12/06/22. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830398

A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation. / Gao, Zhong; Fritz, Martin; He, Jingchu et al.
2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. IEEE, 2022. p. 14-15 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2022-June).

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation

AU - Gao, Zhong

AU - Fritz, Martin

AU - He, Jingchu

AU - Spalink, Gerd

AU - Staszewski, Robert Bogdan

AU - Alavi, Morteza S.

AU - Babaie, Masoud

N1 - Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

PY - 2022

Y1 - 2022

N2 - We present a broadband digital PLL (DPLL)-based phase modulator supporting wide frequency modulation (FM) bandwidth (BW). It compensates for the EVM degradation due to the non-uniform period of the retimed updating clock and shortens the nonlinearity calibration time of the digitally controlled oscillator (DCO) with a phase-domain digital pre-distortion (DPD) and an encoding-assisted (EA)-LMS calibration. While generating a 10MHz 64-PSK signal, the prototype can achieve -46dB EVM with less than one-tenth of the calibration samples (time) required by the prior art.

AB - We present a broadband digital PLL (DPLL)-based phase modulator supporting wide frequency modulation (FM) bandwidth (BW). It compensates for the EVM degradation due to the non-uniform period of the retimed updating clock and shortens the nonlinearity calibration time of the digitally controlled oscillator (DCO) with a phase-domain digital pre-distortion (DPD) and an encoding-assisted (EA)-LMS calibration. While generating a 10MHz 64-PSK signal, the prototype can achieve -46dB EVM with less than one-tenth of the calibration samples (time) required by the prior art.

UR - http://www.scopus.com/inward/record.url?scp=85135204103&partnerID=8YFLogxK

U2 - 10.1109/VLSITechnologyandCir46769.2022.9830398

DO - 10.1109/VLSITechnologyandCir46769.2022.9830398

M3 - Conference contribution

AN - SCOPUS:85135204103

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 14

EP - 15

BT - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022

PB - IEEE

T2 - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022

Y2 - 12 June 2022 through 17 June 2022

ER -

Gao Z, Fritz M, He J, Spalink G, Staszewski RB , Alavi MS et al. A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation. In 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. IEEE. 2022. p. 14-15. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSITechnologyandCir46769.2022.9830398

A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation

Abstract

Publication series

Conference

Bibliographical note

Access to Document

Other files and links

Fingerprint

Cite this