A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration

Bangan Liu, Yuncheng Zhang, Junjun Qiu, Huy Cu Ngo, Wei Deng, Kengo Nakata, Toru Yoshioka, Jun Emmei, Jian Pang, Teruki Someya, More Authors

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Abstract

In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-N multiplying delay-locked loop,(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To calibrate the DTC nonlinearity, a highly robust zero-order interpolation based nonlinearity calibration is proposed. Besides, the static phase offsets,(SPO) between bang-bang phase detector,(BBPD) and multiplexer,(MUX) are calibrated by a proposed hybrid analog/digital phase offset calibration, while the dynamic phase offsets,(DPO) are removed by a proposed complementary switching scheme. The co-design of the analog circuits and digital calibrations enable excellent jitter and spur performance. The MDLL achieves 0.70 and 0.48,ps root-mean-square,(RMS) jitter in fractional-N and integer-N modes, respectively. The fractional spur is less than -59.0,dBc, and the reference spur is -64.5,dBc. The power consumptions are 1.85,mW and 1.22,mW, corresponding to figures of merit,(FOM) of -240.4,dB and -245.5,dB.

Original languageEnglish
Article number9258394
Pages (from-to)603 - 616
Number of pages14
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume68
Issue number2
DOIs
Publication statusPublished - 2021

Keywords

  • Multiplying delay-locked loop (MDLL)
  • bang-bang phase detector (BBPD)
  • digital-to-time converter (DTC)
  • fully-synthesizable
  • injection locking
  • nonlinearity calibration
  • path-selection DTC
  • phase offset
  • phase-locked loop (PLL)
  • variable-slope DTC

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