A study of graphene nanoribbon-based gate performance robustness under temperature variations

As CMOS scaling is reaching its limits, high power density and leakage, low reliability, and increasing IC production costs are prompting for developing new materials, devices, architectures, and computation paradigms. Additionally, temperature variations have a significant impact on devices and circuits reliability and performance. Graphene's remarkable properties make it a promising post Silicon frontrunner for carbon-based nanoelectronics. While for CMOS gates temperature effects have been largely investigated, for gates implemented with atomic-level Graphene Nanoribbons (GNRs), such effects have not been explored. This paper presents the results of such an analysis performed on a set of GNR-based Boolean gates by varying the operation temperature within the military range, i.e., -55°C to 125°C, and evaluating by means of SPICE simulations gate output signal integrity, propagation delay, and power consumption. Our simulation results reveal that GNR-based gates are robust with respect to temperature variation, e.g., 5.2% and 5.3% maximum variations of NAND output logic '1' (VOH) and logic '0' ($V$OL) voltage levels, respectively. Moreover, even in the worst condition GNR-based gates outperform CMOS FinFET 7nm counterparts, e.g., 1.6× smaller delay and 185× less power consumption for the INV case, which is strengthening their great potential as basic building blocks for future reliable, low-power, nanoscale carbon-based electronics.