TY - GEN
T1 - A Subthreshold Source-Coupled Logic based Time-Domain Comparator for SAR ADC based Cardiac Front-Ends
AU - Rout, Samprajani
AU - Babayan-Mashhadi, Samaneh
AU - Serdijn, Wouter A.
PY - 2019/11/1
Y1 - 2019/11/1
N2 - Low-voltage and low-power front-end design is required for the safe and long-term monitoring of cardiac signals. To address the low-voltage challenge, this paper presents a subthreshold source-coupled logic (STSCL) based time-domain comparator designed in 180 nm CMOS process technology. At a low supply voltage of 0.8 V, the STSCL time-domain comparator consumes 2.3 μW at 1 MHz. Using 4 stages, the input referred noise and the offset of the comparator are 32 μVrms and 1.8 mV, respectively.
AB - Low-voltage and low-power front-end design is required for the safe and long-term monitoring of cardiac signals. To address the low-voltage challenge, this paper presents a subthreshold source-coupled logic (STSCL) based time-domain comparator designed in 180 nm CMOS process technology. At a low supply voltage of 0.8 V, the STSCL time-domain comparator consumes 2.3 μW at 1 MHz. Using 4 stages, the input referred noise and the offset of the comparator are 32 μVrms and 1.8 mV, respectively.
KW - biosignal acquisition
KW - low-voltage
KW - source-coupled logic
KW - time-domain comparator
UR - http://www.scopus.com/inward/record.url?scp=85078704605&partnerID=8YFLogxK
U2 - 10.1109/APCCAS47518.2019.8953136
DO - 10.1109/APCCAS47518.2019.8953136
M3 - Conference contribution
T3 - Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption
SP - 17
EP - 20
BT - Proceedings - APCCAS 2019
PB - Institute of Electrical and Electronics Engineers (IEEE)
T2 - 15th Annual IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2019
Y2 - 11 November 2019 through 14 November 2019
ER -
