A Subthreshold Source-Coupled Logic based Time-Domain Comparator for SAR ADC based Cardiac Front-Ends

Samprajani Rout, Samaneh Babayan-Mashhadi, Wouter A. Serdijn

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

1 Citation (Scopus)
19 Downloads (Pure)

Abstract

Low-voltage and low-power front-end design is required for the safe and long-term monitoring of cardiac signals. To address the low-voltage challenge, this paper presents a subthreshold source-coupled logic (STSCL) based time-domain comparator designed in 180 nm CMOS process technology. At a low supply voltage of 0.8 V, the STSCL time-domain comparator consumes 2.3 μW at 1 MHz. Using 4 stages, the input referred noise and the offset of the comparator are 32 μVrms and 1.8 mV, respectively.

Original languageEnglish
Title of host publicationProceedings - APCCAS 2019
Subtitle of host publication2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages17-20
Number of pages4
ISBN (Electronic)9781728129402
DOIs
Publication statusPublished - 1 Nov 2019
Event15th Annual IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2019 - Bangkok, Thailand
Duration: 11 Nov 201914 Nov 2019

Publication series

NameProceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption

Conference

Conference15th Annual IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2019
CountryThailand
CityBangkok
Period11/11/1914/11/19

Keywords

  • biosignal acquisition
  • low-voltage
  • source-coupled logic
  • time-domain comparator

Fingerprint

Dive into the research topics of 'A Subthreshold Source-Coupled Logic based Time-Domain Comparator for SAR ADC based Cardiac Front-Ends'. Together they form a unique fingerprint.

Cite this