An advanced cache power model for an embedded processor using SLEEP methodology

Jia Chen; Y Xu; TGRM van Leuken

An advanced cache power model for an embedded processor using SLEEP methodology

Signal Processing Systems

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

Original language	Undefined/Unknown
Title of host publication	Proceedings of the STW program ProRISC 23/11-24/11, Program for Research on Integrated Systems and Circuits
Editors	STW
Place of Publication	Utrecht, NL
Publisher	STW
Pages	247-248
Number of pages	2
ISBN (Print)	90-73461-44-8
Publication status	Published - 2006
Event	ProRISC, 17th Annual Workshop on Circuits, Systems and Signal Processing, Veldhoven, The Netherlands - Utrecht, NL Duration: 23 Nov 2006 → 24 Nov 2006

Publication series

Name
Publisher	STW

Conference

Conference	ProRISC, 17th Annual Workshop on Circuits, Systems and Signal Processing, Veldhoven, The Netherlands
Period	23/11/06 → 24/11/06

Bibliographical note

neo

Keywords

conference contrib. non-refer.
Geen BTA classificatie

Cite this

@inproceedings{cb79740fbcd74828841a9440afa3a89a,

title = "An advanced cache power model for an embedded processor using SLEEP methodology",

keywords = "conference contrib. non-refer., Geen BTA classificatie",

author = "Jia Chen and Y Xu and {van Leuken}, TGRM",

note = "neo; ProRISC, 17th Annual Workshop on Circuits, Systems and Signal Processing, Veldhoven, The Netherlands ; Conference date: 23-11-2006 Through 24-11-2006",

year = "2006",

language = "Undefined/Unknown",

isbn = "90-73461-44-8",

publisher = "STW",

pages = "247--248",

editor = "STW",

booktitle = "Proceedings of the STW program ProRISC 23/11-24/11, Program for Research on Integrated Systems and Circuits",

}

Chen, J, Xu, Y & van Leuken, TGRM 2006, An advanced cache power model for an embedded processor using SLEEP methodology. in STW (ed.), Proceedings of the STW program ProRISC 23/11-24/11, Program for Research on Integrated Systems and Circuits. STW, Utrecht, NL, pp. 247-248, ProRISC, 17th Annual Workshop on Circuits, Systems and Signal Processing, Veldhoven, The Netherlands, 23/11/06.

An advanced cache power model for an embedded processor using SLEEP methodology. / Chen, Jia; Xu, Y; van Leuken, TGRM.
Proceedings of the STW program ProRISC 23/11-24/11, Program for Research on Integrated Systems and Circuits. ed. / STW. Utrecht, NL: STW, 2006. p. 247-248.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - An advanced cache power model for an embedded processor using SLEEP methodology

AU - Chen, Jia

AU - Xu, Y

AU - van Leuken, TGRM

N1 - neo

PY - 2006

Y1 - 2006

KW - conference contrib. non-refer.

KW - Geen BTA classificatie

UR - http://www.stw.nl

M3 - Conference contribution

SN - 90-73461-44-8

SP - 247

EP - 248

BT - Proceedings of the STW program ProRISC 23/11-24/11, Program for Research on Integrated Systems and Circuits

A2 - STW, null

PB - STW

CY - Utrecht, NL

T2 - ProRISC, 17th Annual Workshop on Circuits, Systems and Signal Processing, Veldhoven, The Netherlands

Y2 - 23 November 2006 through 24 November 2006

ER -

An advanced cache power model for an embedded processor using SLEEP methodology

Publication series

Conference

Bibliographical note

Keywords

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Cite this