An advanced cache power model for an embedded processor using SLEEP methodology

Jia Chen, Y Xu, TGRM van Leuken

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Original languageUndefined/Unknown
Title of host publicationProceedings of the STW program ProRISC 23/11-24/11, Program for Research on Integrated Systems and Circuits
Editors STW
Place of PublicationUtrecht, NL
PublisherSTW
Pages247-248
Number of pages2
ISBN (Print)90-73461-44-8
Publication statusPublished - 2006
EventProRISC, 17th Annual Workshop on Circuits, Systems and Signal Processing, Veldhoven, The Netherlands - Utrecht, NL
Duration: 23 Nov 200624 Nov 2006

Publication series

Name
PublisherSTW

Conference

ConferenceProRISC, 17th Annual Workshop on Circuits, Systems and Signal Processing, Veldhoven, The Netherlands
Period23/11/0624/11/06

Keywords

  • conference contrib. non-refer.
  • Geen BTA classificatie

Cite this

Chen, J., Xu, Y., & van Leuken, TGRM. (2006). An advanced cache power model for an embedded processor using SLEEP methodology. In STW (Ed.), Proceedings of the STW program ProRISC 23/11-24/11, Program for Research on Integrated Systems and Circuits (pp. 247-248). STW.