Abstract
Hysteretic behavior has been experimentally observed in graphene-based structures and has a major influence on graphene surface potential and gate field modulation ability. Thus, a graphene electronic transport modelling methodology, which incorporates hysteresis effects is crucial in order to properly assess gated-controlled graphene structures response and performance. To this end, we propose an atomistic-level electronic transport model, which is non restricted to rectangular graphene geometries and captures hysteretic effects caused by near-interfacial traps, provided that interface traps trapping/detrapping time constant and density are known. We apply the model on a rectangular graphene shape and validate our results against experimentally measured drain current vs. top gate voltage hysteresis curves. Moreover, to demonstrate model's versatility we consider two non-rectangular Graphene NanoRibbons (GNRs) and investigate their hysteresis behaviour. Our experiments indicate good agreement between simulated and measured results, which qualifies the model appropriate for traps-aware exploration of the conduction behaviour of graphene-based devices and circuits.
Original language | English |
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Title of host publication | 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings |
Publisher | IEEE |
Pages | 1-5 |
Number of pages | 5 |
Volume | 2019-May |
ISBN (Electronic) | 9781728103976 |
DOIs | |
Publication status | Published - 2019 |
Event | 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan Duration: 26 May 2019 → 29 May 2019 |
Conference
Conference | 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 |
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Country/Territory | Japan |
City | Sapporo |
Period | 26/05/19 → 29/05/19 |
Keywords
- Carbon-Nanoelectronics
- Graphene
- Hysteresis
- Interface traps