Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS

L. Stornaiuolo, M. Rabozzi, M. D. Santambrogio, D. Sciuto, C. B. Ciobanu, G. Stramondo, A. L. Varbanescu

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Abstract

With the increased interest in energy efficiency, a lot of application domains experiment with Field Programmable Gate Arrays (FPGAs), which promise customized hardware accelerators with high-performance and low power consumption. These experiments possible due to the development of High-Level Languages (HLLs) for FPGAs, which permit non-experts in hardware design languages (HDLs) to program reconfigurable hardware for general purpose computing. However, some of the expert knowledge remains difficult to integrate in HLLs, eventually leading to performance loss for HLL-based applications. One example of such a missing feature is the efficient exploitation of the local memories on FPGAs. A solution to address this challenge is PolyMem, an easy-to-use polymorphic parallel memory that uses BRAMs. In this work, we present HLS-PolyMem, the first complete implementation and in-depth evaluation of PolyMem optimized for the Xilinx Design Suite. Our evaluation demonstrates that HLS-PolyMem is a viable alternative to HLS memory partitioning, the current approach for memory parallelism in Vivado HLS. Specifically, we show that PolyMem offers the same performance as HLS partitioning for simple access patterns, and outperforms partitioning as much as 13x when combining multiple access patterns for the same data structure. We further demonstrate the use of PolyMem for two different case studies, highlighting the superior capabilities of HLS-PolyMem in terms of performance, resource utilization, flexibility, and usability. Based on all the evidence provided in this work, we conclude that HLS-PolyMem enables the efficient use of BRAMs as parallel memories, without compromising the HLS level or the achievable performance.

Original languageEnglish
Title of host publicationVLSI-SoC
Subtitle of host publicationDesign and Engineering of Electronics Systems Based on New Computing Paradigms - 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Revised and Extended Selected Papers
EditorsNicola Bombieri, Graziano Pravadelli, Masahiro Fujita, Todd Austin, Ricardo Reis
Place of PublicationCham
PublisherSpringer
Pages53-78
Number of pages26
ISBN (Electronic)978-3-030-23425-6
ISBN (Print)978-3-030-23424-9
DOIs
Publication statusPublished - 2019
Event26th IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, VLSI-SoC 2018 - Verona, Italy
Duration: 8 Oct 201810 Oct 2018

Publication series

NameIFIP Advances in Information and Communication Technology
Volume561
ISSN (Print)1868-4238
ISSN (Electronic)1868-422X

Conference

Conference26th IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, VLSI-SoC 2018
CountryItaly
CityVerona
Period8/10/1810/10/18

Keywords

  • FPGA
  • High-Level Synthesis
  • Polymorphic Parallel Memory

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    Stornaiuolo, L., Rabozzi, M., Santambrogio, M. D., Sciuto, D., Ciobanu, C. B., Stramondo, G., & Varbanescu, A. L. (2019). Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS. In N. Bombieri, G. Pravadelli, M. Fujita, T. Austin, & R. Reis (Eds.), VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Revised and Extended Selected Papers (pp. 53-78). (IFIP Advances in Information and Communication Technology; Vol. 561). Springer. https://doi.org/10.1007/978-3-030-23425-6_4