Capacitive threshold logic: a designer perspective

MD Padure, C Dan, SD Cotofana, M Bodea, S Vassiliadis

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

10 Citations (Scopus)

Original language	Undefined/Unknown
Title of host publication	CAS '99 proceedings. Vol. 1
Place of Publication	S.l.
Publisher	IEEE Society
Pages	81-84
Number of pages	4
ISBN (Print)	0-7803-5139-8
Publication status	Published - 1999
Event	1999 International Semiconductor Conference, Sinaia - S.l. Duration: 5 Oct 1999 → 9 Oct 1999

Name
Publisher	IEEE

Conference	1999 International Semiconductor Conference, Sinaia
Period	5/10/99 → 9/10/99

Keywords

@inproceedings{ea1c329913504d0da0eea9a73dd090a5,

title = "Capacitive threshold logic: a designer perspective",

keywords = "ZX Int.klas.verslagjaar < 2002",

author = "MD Padure and C Dan and SD Cotofana and M Bodea and S Vassiliadis",

year = "1999",

language = "Undefined/Unknown",

isbn = "0-7803-5139-8",

publisher = "IEEE Society",

pages = "81--84",

booktitle = "CAS '99 proceedings. Vol. 1",

note = "null ; Conference date: 05-10-1999 Through 09-10-1999",

}

TY - GEN

T1 - Capacitive threshold logic: a designer perspective

AU - Padure, MD

AU - Dan, C

AU - Cotofana, SD

AU - Bodea, M

AU - Vassiliadis, S

PY - 1999

Y1 - 1999

KW - ZX Int.klas.verslagjaar < 2002

M3 - Conference contribution

SN - 0-7803-5139-8

SP - 81

EP - 84

BT - CAS '99 proceedings. Vol. 1

PB - IEEE Society

CY - S.l.

Y2 - 5 October 1999 through 9 October 1999

ER -