Circuit arrangement, time-mode arithmetic unit, all-digital phase-locked loop, and corresponding methods

R.B. Staszewski (Inventor), M. Babaie (Inventor), S.M. Alavi (Inventor), Z. Gao (Inventor)

Research output: Patent

Original languageEnglish
IPCH03L, G04F
Publication statusPublished - 2023

Bibliographical note

Patent: OCT-21-064
Applicant: Sony Europe B.V. Zweigniederlassung Deutschland

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