Evaluation methodology for single electron encoded threshold logic gates

CR Lageweg; SD Cotofana; S Vassiliadis

Evaluation methodology for single electron encoded threshold logic gates

CR Lageweg, SD Cotofana, S Vassiliadis

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

Original language	Undefined/Unknown
Title of host publication	VLSI-SoC 2003; IFIP WG 10.5 international conference on very large scale integration of system-on-chip
Editors	M Glesner, R Reis, H Eveking, V Mooney, L Indrusiak, P Zipf
Place of Publication	Darmstadt, Germany
Publisher	Technische Universität Darmstadt
Pages	258-262
Number of pages	5
ISBN (Print)	3-901882-17-0
Publication status	Published - 2003
Event	IFIP WG 10.5 international conference on very large scale integration of system-on-chip, Darmstadt, Germany - Darmstadt, Germany Duration: 1 Dec 2003 → 3 Dec 2003

Publication series

Name
Publisher	Technische Universität Darmstadt

Conference

Conference	IFIP WG 10.5 international conference on very large scale integration of system-on-chip, Darmstadt, Germany
Period	1/12/03 → 3/12/03

Keywords

Conf.proc. > 3 pag

Cite this

Lageweg, CR ; Cotofana, SD ; Vassiliadis, S. / Evaluation methodology for single electron encoded threshold logic gates. VLSI-SoC 2003; IFIP WG 10.5 international conference on very large scale integration of system-on-chip. editor / M Glesner ; R Reis ; H Eveking ; V Mooney ; L Indrusiak ; P Zipf. Darmstadt, Germany : Technische Universität Darmstadt, 2003. pp. 258-262

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title = "Evaluation methodology for single electron encoded threshold logic gates",

keywords = "Conf.proc. > 3 pag",

author = "CR Lageweg and SD Cotofana and S Vassiliadis",

year = "2003",

language = "Undefined/Unknown",

isbn = "3-901882-17-0",

publisher = "Technische Universit{\"a}t Darmstadt",

pages = "258--262",

editor = "M Glesner and R Reis and H Eveking and V Mooney and L Indrusiak and P Zipf",

booktitle = "VLSI-SoC 2003; IFIP WG 10.5 international conference on very large scale integration of system-on-chip",

note = "IFIP WG 10.5 international conference on very large scale integration of system-on-chip, Darmstadt, Germany ; Conference date: 01-12-2003 Through 03-12-2003",

}

Lageweg, CR, Cotofana, SD & Vassiliadis, S 2003, Evaluation methodology for single electron encoded threshold logic gates. in M Glesner, R Reis, H Eveking, V Mooney, L Indrusiak & P Zipf (eds), VLSI-SoC 2003; IFIP WG 10.5 international conference on very large scale integration of system-on-chip. Technische Universität Darmstadt, Darmstadt, Germany, pp. 258-262, IFIP WG 10.5 international conference on very large scale integration of system-on-chip, Darmstadt, Germany, 1/12/03.

Evaluation methodology for single electron encoded threshold logic gates. / Lageweg, CR; Cotofana, SD; Vassiliadis, S.
VLSI-SoC 2003; IFIP WG 10.5 international conference on very large scale integration of system-on-chip. ed. / M Glesner; R Reis; H Eveking; V Mooney; L Indrusiak; P Zipf. Darmstadt, Germany: Technische Universität Darmstadt, 2003. p. 258-262.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Evaluation methodology for single electron encoded threshold logic gates

AU - Lageweg, CR

AU - Cotofana, SD

AU - Vassiliadis, S

PY - 2003

Y1 - 2003

KW - Conf.proc. > 3 pag

M3 - Conference contribution

SN - 3-901882-17-0

SP - 258

EP - 262

BT - VLSI-SoC 2003; IFIP WG 10.5 international conference on very large scale integration of system-on-chip

A2 - Glesner, M

A2 - Reis, R

A2 - Eveking, H

A2 - Mooney, V

A2 - Indrusiak, L

A2 - Zipf, P

PB - Technische Universität Darmstadt

CY - Darmstadt, Germany

T2 - IFIP WG 10.5 international conference on very large scale integration of system-on-chip, Darmstadt, Germany

Y2 - 1 December 2003 through 3 December 2003

ER -