Evaluation methodology for single electron encoded threshold logic gates

CR Lageweg, SD Cotofana, S Vassiliadis

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Original languageUndefined/Unknown
Title of host publicationVLSI-SoC 2003; IFIP WG 10.5 international conference on very large scale integration of system-on-chip
EditorsM Glesner, R Reis, H Eveking, V Mooney, L Indrusiak, P Zipf
Place of PublicationDarmstadt, Germany
PublisherTechnische Universität Darmstadt
Pages258-262
Number of pages5
ISBN (Print)3-901882-17-0
Publication statusPublished - 2003
EventIFIP WG 10.5 international conference on very large scale integration of system-on-chip, Darmstadt, Germany - Darmstadt, Germany
Duration: 1 Dec 20033 Dec 2003

Publication series

Name
PublisherTechnische Universität Darmstadt

Conference

ConferenceIFIP WG 10.5 international conference on very large scale integration of system-on-chip, Darmstadt, Germany
Period1/12/033/12/03

Keywords

  • Conf.proc. > 3 pag

Cite this

Lageweg, CR., Cotofana, SD., & Vassiliadis, S. (2003). Evaluation methodology for single electron encoded threshold logic gates. In M. Glesner, R. Reis, H. Eveking, V. Mooney, L. Indrusiak, & P. Zipf (Eds.), VLSI-SoC 2003; IFIP WG 10.5 international conference on very large scale integration of system-on-chip (pp. 258-262). Technische Universität Darmstadt.