Hardware acceleration of BWA-MEM genomic short read mapping for longer read lengths

Ernst Joachim Houtgast*, Vlad-Mihai Sima, Koen Bertels, Zaid Al-Ars

*Corresponding author for this work

Research output: Contribution to journalArticleScientificpeer-review

81 Citations (Scopus)
157 Downloads (Pure)


We present our work on hardware accelerated genomics pipelines, using either FPGAs or GPUs to accelerate execution of BWA-MEM, a widely-used algorithm for genomic short read mapping. The mapping stage can take up to 40% of overall processing time for genomics pipelines. Our implementation offloads the Seed Extension function, one of the main BWA-MEM computational functions, onto an accelerator. Sequencers typically output reads with a length of 150 base pairs. However, read length is expected to increase in the near future. Here, we investigate the influence of read length on BWA-MEM performance using data sets with read length up to 400 base pairs, and introduce methods to ameliorate the impact of longer read length. For the industry-standard 150 base pair read length, our implementation achieves an up to two-fold increase in overall application-level performance for systems with at most twenty-two logical CPU cores. Longer read length requires commensurately bigger data structures, which directly impacts accelerator efficiency. The two-fold performance increase is sustained for read length of at most 250 base pairs. To improve performance, we perform a classification of the inefficiency of the underlying systolic array architecture. By eliminating idle regions as much as possible, efficiency is improved by up to +95%. Moreover, adaptive load balancing intelligently distributes work between host and accelerator to ensure use of an accelerator always results in performance improvement, which in GPU-constrained scenarios provides up to +45% more performance.

Original languageEnglish
Pages (from-to)54-64
Number of pages11
JournalComputational Biology and Chemistry
Publication statusPublished - 2018

Bibliographical note

Accepted author manuscript


  • Acceleration
  • FPGA
  • GPU
  • Short read mapping
  • Systolic array


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