Low Area Overhead Custom Buffering for FFT

Nils Voss, Stephen Girdlestone, Tobias Becker, Oskar Mencer, Wayne Luk, Georgi Gaydadjiev

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

2 Citations (Scopus)

Abstract

In this paper we propose a technique to minimise the area overhead of a double buffered implementation of Radix-4 Fast Fourier Transformation (FFT). Our proposal circumvents the need for double buffering by exploiting opportunities in the specific data reordering of the buffers that are needed when implementing a fully pipelined FFT. By using the same read and write pattern, a single buffer is sufficient to perform data reordering while maintaining data integrity without degrading performance. We demonstrate this approach in an FPGA implementation. As a result of our optimisation, the memory depth can be reduced by a factor of two with very small overhead in control logic complexity.

Original languageEnglish
Title of host publication2019 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2019
EditorsDavid Andrews, Rene Cumplido, Claudia Feregrino, Marco Platzner
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
ISBN (Electronic)9781728119571
DOIs
Publication statusPublished - Dec 2019
Externally publishedYes
Event2019 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2019 - Cancun, Mexico
Duration: 9 Dec 201911 Dec 2019

Publication series

Name2019 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2019

Conference

Conference2019 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2019
Country/TerritoryMexico
CityCancun
Period9/12/1911/12/19

Keywords

  • Double Buffering
  • FFT
  • FPGA
  • On-Chip Memory
  • Optimisation
  • Transpose

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