Current monolithic quantum computer architectures have limited scalability. One promising approach for scaling them up is to use a modular or multi-core architecture, in which different quantum processors (cores) are connected via quantum and classical links. This new architectural design poses new challenges such as the expensive inter-core communication. To reduce these movements when executing a quantum algorithm, an efficient mapping technique is required. In this paper, a detailed critical discussion of the quantum circuit mapping problem for multi-core quantum computing architectures is provided. In addition, we further explore the performance of a mapping method, which is formulated as a partitioning over time graph problem, by performing an architectural scalability analysis.
|Title of host publication||ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Number of pages||5|
|Publication status||Published - 2023|
|Event||56th IEEE International Symposium on Circuits and Systems, ISCAS 2023 - Monterey, United States|
Duration: 21 May 2023 → 25 May 2023
|Name||Proceedings - IEEE International Symposium on Circuits and Systems|
|Conference||56th IEEE International Symposium on Circuits and Systems, ISCAS 2023|
|Period||21/05/23 → 25/05/23|
Bibliographical noteGreen Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.
- mapping of quantum algorithms
- multi-core quantum computers
- scalability quantum computing systems