MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array

Carlos Escuin; Fernando García-Redondo; Mahdi Zahedi; Pablo Ibáñez; Teresa Monreal; Victor Viñals; José María  Llabería; James Myers; Julien Ryckaert; Dwaipayan  Biswas; Francky Catthoor

doi:10.1109/ICECS58634.2023.10382874

MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array

Carlos Escuin, Fernando García-Redondo, Mahdi Zahedi, Pablo Ibáñez, Teresa Monreal, Victor Viñals, José María Llabería, James Myers, Julien Ryckaert, Dwaipayan Biswas, Francky Catthoor

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

Abstract

This paper optimizes the MNEMOSENE architecture, a compute-in-memory (CiM) tile design integrating computation and storage for increased efficiency. We identify and address bottlenecks in the Row Data (RD) buffer that cause losses in performance. Our proposed approach includes mitigating these buffering bottlenecks and extending MNEMOSENE’s single-tile design to a multi-tile configuration for improved parallel processing. The proposal is validated through comprehensive analyses exploring the mapping of diverse neural networks evaluated on CiM crossbar arrays based on NVM technologies. These proposed enhancements lead up to 55% reduction in execution time compared to the original single-tile architecture for any general matrix multiplication (GEMM) operation. Our evaluation shows that while ReRAM and PCM offer notable energy advantages, their integration with scaled CMOS is limited, which leads to VGSOT-MRAM emerging as a promising alternative due to its good balance between energy efficiency and superior integration capabilities. The VGSOT-MRAM crossbar arrays provide 12×,49×, and 346× more energy efficiency than PCM, ReRAM, and STT-MRAM ones, respectively. It translates, on average for the considered workload, in 1.5×,3×, and 14.5× better energy efficiency of the entire system.

Original language	English
Title of host publication	Proceedings of the 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
Place of Publication	Piscataway
Publisher	IEEE
Number of pages	5
ISBN (Electronic)	979-8-3503-2649-9
ISBN (Print)	979-8-3503-2650-5
DOIs	https://doi.org/10.1109/ICECS58634.2023.10382874
Publication status	Published - 2023
Event	2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS) - Istanbul, Turkey Duration: 4 Dec 2023 → 7 Dec 2023

Conference

Conference	2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
Country/Territory	Turkey
City	Istanbul
Period	4/12/23 → 7/12/23

Bibliographical note

Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care
Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Keywords

Compute in Memory
NVM
Memristor
MRAM
Convolutional Neural Networks
Machine Learning

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ICECS58634.2023.10382874

Cite this

Escuin, C., García-Redondo, F., Zahedi, M., Ibáñez, P., Monreal, T., Viñals, V., Llabería, J. M., Myers, J., Ryckaert, J., Biswas, D., & Catthoor, F. (2023). MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array. In Proceedings of the 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS) IEEE. https://doi.org/10.1109/ICECS58634.2023.10382874

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abstract = "This paper optimizes the MNEMOSENE architecture, a compute-in-memory (CiM) tile design integrating computation and storage for increased efficiency. We identify and address bottlenecks in the Row Data (RD) buffer that cause losses in performance. Our proposed approach includes mitigating these buffering bottlenecks and extending MNEMOSENE{\textquoteright}s single-tile design to a multi-tile configuration for improved parallel processing. The proposal is validated through comprehensive analyses exploring the mapping of diverse neural networks evaluated on CiM crossbar arrays based on NVM technologies. These proposed enhancements lead up to 55% reduction in execution time compared to the original single-tile architecture for any general matrix multiplication (GEMM) operation. Our evaluation shows that while ReRAM and PCM offer notable energy advantages, their integration with scaled CMOS is limited, which leads to VGSOT-MRAM emerging as a promising alternative due to its good balance between energy efficiency and superior integration capabilities. The VGSOT-MRAM crossbar arrays provide 12×,49×, and 346× more energy efficiency than PCM, ReRAM, and STT-MRAM ones, respectively. It translates, on average for the considered workload, in 1.5×,3×, and 14.5× better energy efficiency of the entire system.",

keywords = "Compute in Memory, NVM, Memristor, MRAM, Convolutional Neural Networks, Machine Learning",

author = "Carlos Escuin and Fernando Garc{\'i}a-Redondo and Mahdi Zahedi and Pablo Ib{\'a}{\~n}ez and Teresa Monreal and Victor Vi{\~n}als and Llaber{\'i}a, {Jos{\'e} Mar{\'i}a} and James Myers and Julien Ryckaert and Dwaipayan Biswas and Francky Catthoor",

note = "Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.; 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS) ; Conference date: 04-12-2023 Through 07-12-2023",

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language = "English",

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Escuin, C, García-Redondo, F, Zahedi, M, Ibáñez, P, Monreal, T, Viñals, V, Llabería, JM, Myers, J, Ryckaert, J, Biswas, D & Catthoor, F 2023, MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array. in Proceedings of the 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS). IEEE, Piscataway, 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Istanbul, Turkey, 4/12/23. https://doi.org/10.1109/ICECS58634.2023.10382874

MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array. / Escuin, Carlos; García-Redondo, Fernando; Zahedi, Mahdi et al.
Proceedings of the 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS). Piscataway: IEEE, 2023.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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T1 - MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array

AU - Escuin, Carlos

AU - García-Redondo, Fernando

AU - Zahedi, Mahdi

AU - Ibáñez, Pablo

AU - Monreal, Teresa

AU - Viñals, Victor

AU - Llabería, José María

AU - Myers, James

AU - Ryckaert, Julien

AU - Biswas, Dwaipayan

AU - Catthoor, Francky

N1 - Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

PY - 2023

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N2 - This paper optimizes the MNEMOSENE architecture, a compute-in-memory (CiM) tile design integrating computation and storage for increased efficiency. We identify and address bottlenecks in the Row Data (RD) buffer that cause losses in performance. Our proposed approach includes mitigating these buffering bottlenecks and extending MNEMOSENE’s single-tile design to a multi-tile configuration for improved parallel processing. The proposal is validated through comprehensive analyses exploring the mapping of diverse neural networks evaluated on CiM crossbar arrays based on NVM technologies. These proposed enhancements lead up to 55% reduction in execution time compared to the original single-tile architecture for any general matrix multiplication (GEMM) operation. Our evaluation shows that while ReRAM and PCM offer notable energy advantages, their integration with scaled CMOS is limited, which leads to VGSOT-MRAM emerging as a promising alternative due to its good balance between energy efficiency and superior integration capabilities. The VGSOT-MRAM crossbar arrays provide 12×,49×, and 346× more energy efficiency than PCM, ReRAM, and STT-MRAM ones, respectively. It translates, on average for the considered workload, in 1.5×,3×, and 14.5× better energy efficiency of the entire system.

AB - This paper optimizes the MNEMOSENE architecture, a compute-in-memory (CiM) tile design integrating computation and storage for increased efficiency. We identify and address bottlenecks in the Row Data (RD) buffer that cause losses in performance. Our proposed approach includes mitigating these buffering bottlenecks and extending MNEMOSENE’s single-tile design to a multi-tile configuration for improved parallel processing. The proposal is validated through comprehensive analyses exploring the mapping of diverse neural networks evaluated on CiM crossbar arrays based on NVM technologies. These proposed enhancements lead up to 55% reduction in execution time compared to the original single-tile architecture for any general matrix multiplication (GEMM) operation. Our evaluation shows that while ReRAM and PCM offer notable energy advantages, their integration with scaled CMOS is limited, which leads to VGSOT-MRAM emerging as a promising alternative due to its good balance between energy efficiency and superior integration capabilities. The VGSOT-MRAM crossbar arrays provide 12×,49×, and 346× more energy efficiency than PCM, ReRAM, and STT-MRAM ones, respectively. It translates, on average for the considered workload, in 1.5×,3×, and 14.5× better energy efficiency of the entire system.

KW - Compute in Memory

KW - NVM

KW - Memristor

KW - MRAM

KW - Convolutional Neural Networks

KW - Machine Learning

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DO - 10.1109/ICECS58634.2023.10382874

M3 - Conference contribution

SN - 979-8-3503-2650-5

BT - Proceedings of the 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

PB - IEEE

CY - Piscataway

T2 - 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

Y2 - 4 December 2023 through 7 December 2023

ER -

MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array

Abstract

Conference

Bibliographical note

Keywords

UN SDGs

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