PetaOps/W edge-AI μ Processors: Myth or reality?

Manil Dev  Gomony; Floran  de Putter; Anteneh  Gebregiorgis; Gianna  Paulin; Linyan  Mei; Vikram  Jain; Said Hamdioui; Rajendra Bishnoi; Victor Sanchez; null More Authors

doi:10.23919/DATE56975.2023.10136926

PetaOps/W edge-AI μ Processors: Myth or reality?

Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Rajendra Bishnoi, Victor Sanchez, More Authors

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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Abstract

With the rise of deep learning (DL), our world braces for artificial intelligence (AI) in every edge device, creating an urgent need for edge-AI SoCs. This SoC hardware needs to support high throughput, reliable and secure AI processing at ultra-low power (ULP), with a very short time to market. With its strong legacy in edge solutions and open processing platforms, the EU is well-positioned to become a leader in this SoC market. However, this requires AI edge processing to become at least 100 times more energy-efficient, while offering sufficient flexibility and scalability to deal with AI as a fast-moving target. Since the design space of these complex SoCs is huge, advanced tooling is needed to make their design tractable. The CONVOLVE project (currently in Inital stage) addresses these roadblocks. It takes a holistic approach with innovations at all levels of the design hierarchy. Starting with an overview of SOTA DL processing support and our project methodology, this paper presents 8 important design choices largely impacting the energy efficiency and flexibility of DL hardware. Finding good solutions is key to making smart-edge computing a reality.

Original language	English
Title of host publication	Proceedings of the 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Place of Publication	Piscataway
Publisher	IEEE
Pages	1-6
Number of pages	6
ISBN (Print)	979-8-3503-9624-9
DOIs	https://doi.org/10.23919/DATE56975.2023.10136926
Publication status	Published - 2023
Event	DATE 2023: Design, Automation & Test in Europe Conference & Exhibition - Antwerp, Belgium Duration: 17 Apr 2023 → 19 Apr 2023 https://www.date-conference.com

Conference

Conference	DATE 2023
Country/Territory	Belgium
City	Antwerp
Period	17/04/23 → 19/04/23
Internet address	https://www.date-conference.com

Bibliographical note

Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care
Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Keywords

ULP
dynamic DL
edge-AI
SoC
memristor
approximate computing
DSE
compiler stack

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.23919/DATE56975.2023.10136926

PetaOps_W_edge-AI_mu_Processors_Myth_or_realityFinal published version, 9.15 MB

Cite this

@inproceedings{fd2a28677b584ded862875b7e54514cf,

title = "PetaOps/W edge-AI μ Processors: Myth or reality? ",

abstract = "With the rise of deep learning (DL), our world braces for artificial intelligence (AI) in every edge device, creating an urgent need for edge-AI SoCs. This SoC hardware needs to support high throughput, reliable and secure AI processing at ultra-low power (ULP), with a very short time to market. With its strong legacy in edge solutions and open processing platforms, the EU is well-positioned to become a leader in this SoC market. However, this requires AI edge processing to become at least 100 times more energy-efficient, while offering sufficient flexibility and scalability to deal with AI as a fast-moving target. Since the design space of these complex SoCs is huge, advanced tooling is needed to make their design tractable. The CONVOLVE project (currently in Inital stage) addresses these roadblocks. It takes a holistic approach with innovations at all levels of the design hierarchy. Starting with an overview of SOTA DL processing support and our project methodology, this paper presents 8 important design choices largely impacting the energy efficiency and flexibility of DL hardware. Finding good solutions is key to making smart-edge computing a reality.",

keywords = "ULP, dynamic DL, edge-AI, SoC, memristor, approximate computing, DSE, compiler stack",

author = "Gomony, {Manil Dev} and {de Putter}, Floran and Anteneh Gebregiorgis and Gianna Paulin and Linyan Mei and Vikram Jain and Said Hamdioui and Rajendra Bishnoi and Victor Sanchez and {More Authors}",

note = "Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.; DATE 2023 : Design, Automation & Test in Europe Conference & Exhibition ; Conference date: 17-04-2023 Through 19-04-2023",

year = "2023",

doi = "10.23919/DATE56975.2023.10136926",

language = "English",

isbn = "979-8-3503-9624-9",

pages = "1--6",

booktitle = "Proceedings of the 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)",

publisher = "IEEE",

address = "United States",

url = "https://www.date-conference.com",

}

Gomony, MD, de Putter, F, Gebregiorgis, A, Paulin, G, Mei, L, Jain, V, Hamdioui, S , Bishnoi, R, Sanchez, V & More Authors 2023, PetaOps/W edge-AI μ Processors: Myth or reality? . in Proceedings of the 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, Piscataway, pp. 1-6, DATE 2023, Antwerp, Belgium, 17/04/23. https://doi.org/10.23919/DATE56975.2023.10136926

PetaOps/W edge-AI μ Processors: Myth or reality? . / Gomony, Manil Dev; de Putter, Floran ; Gebregiorgis, Anteneh et al.
Proceedings of the 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE). Piscataway: IEEE, 2023. p. 1-6.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - PetaOps/W edge-AI μ Processors

T2 - DATE 2023

AU - Gomony, Manil Dev

AU - de Putter, Floran

AU - Gebregiorgis, Anteneh

AU - Paulin, Gianna

AU - Mei, Linyan

AU - Jain, Vikram

AU - Hamdioui, Said

AU - Bishnoi, Rajendra

AU - Sanchez, Victor

AU - More Authors, null

N1 - Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

PY - 2023

Y1 - 2023

N2 - With the rise of deep learning (DL), our world braces for artificial intelligence (AI) in every edge device, creating an urgent need for edge-AI SoCs. This SoC hardware needs to support high throughput, reliable and secure AI processing at ultra-low power (ULP), with a very short time to market. With its strong legacy in edge solutions and open processing platforms, the EU is well-positioned to become a leader in this SoC market. However, this requires AI edge processing to become at least 100 times more energy-efficient, while offering sufficient flexibility and scalability to deal with AI as a fast-moving target. Since the design space of these complex SoCs is huge, advanced tooling is needed to make their design tractable. The CONVOLVE project (currently in Inital stage) addresses these roadblocks. It takes a holistic approach with innovations at all levels of the design hierarchy. Starting with an overview of SOTA DL processing support and our project methodology, this paper presents 8 important design choices largely impacting the energy efficiency and flexibility of DL hardware. Finding good solutions is key to making smart-edge computing a reality.

AB - With the rise of deep learning (DL), our world braces for artificial intelligence (AI) in every edge device, creating an urgent need for edge-AI SoCs. This SoC hardware needs to support high throughput, reliable and secure AI processing at ultra-low power (ULP), with a very short time to market. With its strong legacy in edge solutions and open processing platforms, the EU is well-positioned to become a leader in this SoC market. However, this requires AI edge processing to become at least 100 times more energy-efficient, while offering sufficient flexibility and scalability to deal with AI as a fast-moving target. Since the design space of these complex SoCs is huge, advanced tooling is needed to make their design tractable. The CONVOLVE project (currently in Inital stage) addresses these roadblocks. It takes a holistic approach with innovations at all levels of the design hierarchy. Starting with an overview of SOTA DL processing support and our project methodology, this paper presents 8 important design choices largely impacting the energy efficiency and flexibility of DL hardware. Finding good solutions is key to making smart-edge computing a reality.

KW - ULP

KW - dynamic DL

KW - edge-AI

KW - SoC

KW - memristor

KW - approximate computing

KW - DSE

KW - compiler stack

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U2 - 10.23919/DATE56975.2023.10136926

DO - 10.23919/DATE56975.2023.10136926

M3 - Conference contribution

SN - 979-8-3503-9624-9

SP - 1

EP - 6

BT - Proceedings of the 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)

PB - IEEE

CY - Piscataway

Y2 - 17 April 2023 through 19 April 2023

ER -

PetaOps/W edge-AI μ Processors: Myth or reality?

Abstract

Conference

Bibliographical note

Keywords

UN SDGs

Access to Document

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Cite this