Abstract
This article presents a chip multiprocessor (CMP) design that mixes coarse- and fine-grained reconfigurability to increase core availability of safety-critical embedded systems in the presence of hard errors. The authors conducted a comprehensive design-space exploration to identify the granularity mixes that maximize CMP fault tolerance and minimize performance and energy overheads. The authors added fine-grained reconfigurable logic to a coarse-grained sparing approach. Their resulting design can tolerate 3 times more hard errors than core redundancy and 1.5 times more than any other purely coarse-grained solution.
Original language | English |
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Article number | 7006345 |
Pages (from-to) | 35-45 |
Number of pages | 11 |
Journal | IEEE Micro |
Volume | 36 |
Issue number | 1 |
DOIs | |
Publication status | Published - 2016 |
Externally published | Yes |
Keywords
- Adaptable architectures
- Availability
- CMP
- Microarchitecture implementation considerations
- Multicore
- Pipeline implementation
- Reconfigurable hardware
- Reliability
- Serviceability
- Single-chip multiprocessor