Ultra low latency dataflow renderer

Sebastian Friston, Anthony Steed, Simon Tilbury, Georgi Gaydadjiev

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

1 Citation (Scopus)

Abstract

Reconfigurable hardware has been used before for low latency image synthesis. These are typically low level implementations with tight vertical integration. For example the apparatus of both Regan et al and Ng et al had the tracker driven by the same device performing the rendering. Reconfigurable hardware combined with the dataflow programming model can make application specific rendering hardware cost effective. Our sprite renderer has comparable scope to both prior examples, but our dataflow graph can be adapted to other use cases with an effort comparable to GPU shader programming.

Original languageEnglish
Title of host publication25th International Conference on Field Programmable Logic and Applications, FPL 2015
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages1-4
Number of pages4
ISBN (Electronic)9780993428005
DOIs
Publication statusPublished - 7 Oct 2015
Externally publishedYes
Event25th International Conference on Field Programmable Logic and Applications, FPL 2015 - London, United Kingdom
Duration: 2 Sep 20154 Sep 2015

Conference

Conference25th International Conference on Field Programmable Logic and Applications, FPL 2015
CountryUnited Kingdom
CityLondon
Period2/09/154/09/15

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