Ultra low latency dataflow renderer

Sebastian Friston; Anthony Steed; Simon Tilbury; Georgi Gaydadjiev

doi:10.1109/FPL.2015.7293974

Ultra low latency dataflow renderer

Sebastian Friston, Anthony Steed, Simon Tilbury, Georgi Gaydadjiev

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

1 Citation (Scopus)

Abstract

Reconfigurable hardware has been used before for low latency image synthesis. These are typically low level implementations with tight vertical integration. For example the apparatus of both Regan et al and Ng et al had the tracker driven by the same device performing the rendering. Reconfigurable hardware combined with the dataflow programming model can make application specific rendering hardware cost effective. Our sprite renderer has comparable scope to both prior examples, but our dataflow graph can be adapted to other use cases with an effort comparable to GPU shader programming.

Original language	English
Title of host publication	25th International Conference on Field Programmable Logic and Applications, FPL 2015
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	1-4
Number of pages	4
ISBN (Electronic)	9780993428005
DOIs	https://doi.org/10.1109/FPL.2015.7293974
Publication status	Published - 7 Oct 2015
Externally published	Yes
Event	25th International Conference on Field Programmable Logic and Applications, FPL 2015 - London, United Kingdom Duration: 2 Sept 2015 → 4 Sept 2015

Conference

Conference	25th International Conference on Field Programmable Logic and Applications, FPL 2015
Country/Territory	United Kingdom
City	London
Period	2/09/15 → 4/09/15

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10.1109/FPL.2015.7293974

Cite this

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title = "Ultra low latency dataflow renderer",

abstract = "Reconfigurable hardware has been used before for low latency image synthesis. These are typically low level implementations with tight vertical integration. For example the apparatus of both Regan et al and Ng et al had the tracker driven by the same device performing the rendering. Reconfigurable hardware combined with the dataflow programming model can make application specific rendering hardware cost effective. Our sprite renderer has comparable scope to both prior examples, but our dataflow graph can be adapted to other use cases with an effort comparable to GPU shader programming.",

author = "Sebastian Friston and Anthony Steed and Simon Tilbury and Georgi Gaydadjiev",

year = "2015",

month = oct,

day = "7",

doi = "10.1109/FPL.2015.7293974",

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pages = "1--4",

booktitle = "25th International Conference on Field Programmable Logic and Applications, FPL 2015",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

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note = "25th International Conference on Field Programmable Logic and Applications, FPL 2015 ; Conference date: 02-09-2015 Through 04-09-2015",

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Friston, S, Steed, A, Tilbury, S & Gaydadjiev, G 2015, Ultra low latency dataflow renderer. in 25th International Conference on Field Programmable Logic and Applications, FPL 2015., 7293974, Institute of Electrical and Electronics Engineers (IEEE), pp. 1-4, 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, 2/09/15. https://doi.org/10.1109/FPL.2015.7293974

Ultra low latency dataflow renderer. / Friston, Sebastian; Steed, Anthony; Tilbury, Simon et al.
25th International Conference on Field Programmable Logic and Applications, FPL 2015. Institute of Electrical and Electronics Engineers (IEEE), 2015. p. 1-4 7293974.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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Ultra low latency dataflow renderer

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