Wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions for superconducting quantum processors

N. Muthusubramanian, M. Finkel, W.J. Duivestein, C. Zachariadis, S.L.M. van der Meer, H.M. Veen, M.W. Beekman, T. Stavenga, A. Bruno, L. DiCarlo*

*Corresponding author for this work

Research output: Contribution to journalArticleScientificpeer-review

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Abstract

We investigate die-level and wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions, using multiple substrates with and without through-silicon vias (TSVs). Dolan junctions fabricated on planar substrates have the highest yield and lowest room-temperature conductance spread, equivalent to ∼ 100 M H z in transmon frequency. In TSV-integrated substrates, Dolan junctions suffer most in both yield and disorder, making Manhattan junctions preferable. Manhattan junctions show pronounced conductance decrease from wafer center to edge, which we qualitatively capture using a geometric model of spatially-dependent resist shadowing during junction electrode evaporation. Analysis of actual junction overlap areas using scanning electron micrographs supports the model, and further points to a remnant spatial dependence possibly due to contact resistance.

Original languageEnglish
Article number025006
Number of pages12
JournalQuantum Science and Technology
Volume9
Issue number2
DOIs
Publication statusPublished - 2024

Keywords

  • transmon
  • scalability
  • through-silicon vias
  • frequency targeting
  • Dolan-bridge junction
  • Manhattan-style junction

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