A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow

Zhongkai Wang*, Minsoo Choi, John Wright, Kyoungtae Lee, Zhaokai Liu, Bozhi Yin, Jaeduk Han, Sijun Du, Elad Alon

*Corresponding author for this work

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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Abstract

We present a ring-oscillator-based sub-sampling phase-locked loop (PLL) using a generator-based design flow. A hybrid loop with a delta-sigma ($\Delta \Sigma$) modulator is applied to reduce the loop filter (LF) area and the control ripple. The generator automatically produces the ring oscillator and PLL to meet the provided specifications. The 10-GHz PLL instance implemented in 28-nm planar process achieves RMS jitter of}299.5 fs and power of 9.9 mW from a 1-V supply.
Original languageEnglish
Title of host publicationProceedings of the 2022 IEEE International Symposium on Circuits and Systems (ISCAS)
Place of PublicationDanvers
PublisherIEEE
Pages2881-2885
Number of pages5
ISBN (Electronic)978-1-6654-8485-5
ISBN (Print)978-1-6654-8486-2
DOIs
Publication statusPublished - 2022
Event2022 IEEE International Symposium on Circuits and Systems (ISCAS) - Austin, United States
Duration: 27 May 20221 Jun 2022

Conference

Conference2022 IEEE International Symposium on Circuits and Systems (ISCAS)
Country/TerritoryUnited States
CityAustin
Period27/05/221/06/22

Bibliographical note

Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care

Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Keywords

  • PLL
  • sub-sampling
  • ring oscillator
  • hybrid
  • PLL generator

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